Low-cost FPGA stereo vision system for real time disparity maps calculation
- 作者：Paolo Zicari ; [Author Vitae] ; Stefania Perri ; [Author Vitae] ; Pasquale Corsonello ; p.corsonello@unical.it ; [Author Vitae] ; Giuseppe Cocorullo ; [Author Vitae]
- 关键词：Stereo vision ; FPGA ; Low-cost architecture ; VLSI implementation
- 刊名：Microprocessors and Microsystems
- 出版年：2012
- 期刊代码：129_01419331
- 类别：et
- 出版时间：June, 2012
- 卷：36
- 期：4
- 页码：281-288
- 文件大小：731 K
摘要
Several applications demand efficient hardware implementations of stereo vision systems in order to furnish real time three-dimensional measurements. This paper proposes a complete fast low-cost stereo vision system that performs stereo image rectification with tangential and radial distortion removal, computes dense disparity maps using the Sum of Absolute Differences as the dissimilarity metric, and, finally, exploits a novel injective consistency check purpose-designed for eliminating unreliable disparity values.
The proposed system has been realized and hardware tested for several images resolutions and disparity ranges. When 1280 脳 720 grayscale images are processed with the disparity range equal to 30, the system allows a frame rate up to 97 fps@89 MHz to be reached. It has been realized on a single low-cost XilinxVirtex-4 XC4VLX60 FPGA chip and it occupies 63 DSPs, 128 BRAMs and 15728 slices.