Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2<sup>msup>) Generated by AOPs
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- 作者：J.L. Ima帽a and J.M. S谩nchez
- 关键词：Galois field GF(2m) ; canonical basis ; normal basis ; bit ; parallel multiplier ; reconfigurable hardware
- 刊名：The Journal of VLSI Signal Processing
- 出版时间：March 2006
- 出版年：2006
- 期刊代码：26_09225773
- 类别：soc
- 卷：42
- 期：3
- 页码：285-296
- 数据来源：sp
摘要
Galois fields GF(2m) are used in modern communication systems such as computer networks, satellite links, or compact disks, and they play an important role in a wide number of technical applications. They use arithmetic operations in the Galois field, where the multiplication is the most important and one of the most complex operations. Efficient multiplier architectures are therefore specially important. In this paper, a new method for multiplication in the canonical and normal basis over GF(2m) generated by an AOP (all-one-polynomial), which we have named the transpositional method, is presented. This new approach is based on the grouping and sharing of subexpressions. The theoretical space and time complexities of the bit-parallel canonical and normal basis multipliers constructed using our approach are equal to the smallest ones found in the literature for similar methods, but the practical implementation over reconfigurable hardware using our method reduces the area requirements of the multipliers.