摘要
With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34%in area overhead with an average improvement of 65%in delay overhead and 90%in power overhead during normal mode of operation, compared to the enhanced scan implementation.