基于射频收发应用的低噪声频率综合器设计
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摘要
随着无线通信技术的高速发展,载波频段的不断升高,对收发芯片中频率综合器的噪声性能提出了较高的要求。针对通信收发系统中频率综合器的设计,提出了一些低噪声的设计技术,电源电压1.2 V,采用SMIC 0.13μm CMOS工艺。主要对频率综合器主要组成模块鉴相器、电荷泵、LC型压控振荡器以及ΔΣ调制器的噪声性能进行了分析和优化,在此基础上提出了优化相位噪声的方案,并展示了关键模块的仿真结果和整体电路相位噪声的测试情况。结果显示其噪声性能达到了国内较高水平。
The rapid development of wireless communication technology and the higher and higher carrier frequency band put higher demands on the noise performance of the frequency synthesizer in the transceiver chip.For the design of frequency synthesizers in communication transceiver system,some low noise design techniques are proposed.The power supply voltage of the design is 1.2 V,and the process is CMOS 0.13 um.The paper analyzes and optimizes the noise performance of the main components of the frequency synthesizer,including the phase detector,charge pump,LC type oscillator and the ΔΣ modulator.Based on this,the paper proposes the scheme of phase noise optimization and presents the simulation results of key modules and phase noise test results of the whole circuits. The results show that the noise performance has reached the high domestic level.
The rapid development of wireless communication technology and the higher and higher carrier frequency band put higher demands on the noise performance of the frequency synthesizer in the transceiver chip.For the design of frequency synthesizers in communication transceiver system,some low noise design techniques are proposed.The power supply voltage of the design is 1.2 V,and the process is CMOS 0.13 um.The paper analyzes and optimizes the noise performance of the main components of the frequency synthesizer,including the phase detector,charge pump,LC type oscillator and the ΔΣ modulator.Based on this,the paper proposes the scheme of phase noise optimization and presents the simulation results of key modules and phase noise test results of the whole circuits. The results show that the noise performance has reached the high domestic level.
引文
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[2]Sansen W M C.模拟集成电路设计精粹[M].北京:清华大学出版社,2008.
[3]拉扎维.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2008.
[4]Pamarti S,Jansson L,Galton I.A Wideband 2.4 GHz Delta-Sigma Fraetional-N PLL with l-Mb/s In-Loo P Modulation[J].IEEE Journal of Solid-State Circuits,2004,39(1):49-62.
[5]Temporit E,Albasini G,Bietti I,et al.A 700-k Hz BandwidthΔΣFractional Synthesizer with Spurs Compensation and Linearization Techniq-ues for WCDMA Applications[J].IEEE Journal of Solid-State Circuits,2004,39(9):1446-1454.
[6]Swaminathan A,Wang K J,Galton I.A Wide-Bandwidth2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation[J].IEEE Journal of Solid-State Circuits,2007,42(12):2639-2650.
[7]Meninger S E,Perrott M H.A 1-MHz Bandwidth3.6-GHz 0.18-um CMOS Fractional-Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise[J].IEEE Journal of Solid-State Circuits,2006,41(4):966-980.
[8]Hedayati H,Khalil W,Bakkaloglu B.A 1 MHz Bandwidth,6 GHz 0.18 um CMOS Type-IΔΣFractional-N Synthesizer for Wi MAX Application[J].IEEE Journal of Solid-State Circuits,2009,44(12):3244-3252.
[9]何捷.DVB-T接收机中频率综合器的研究[D].上海:上海交通大学,2005.
[10]邓贤进,李家胤,张健.锁相频率合成器相位噪声的精确估计与仿真[J].电路与系统学报,2006,11(5):128-131.
[11]张淑娥,王丹.基于LTC1562的谐振器设计与实现[J].无线电工程,2011,41(11):40-42,60.
[12]刘欣,井科学,欧阳萍.基于YIG振荡器的宽带频率综合器设计[J].无线电工程,2012,42(2):58-61.
[13]彭志华,周存麒.C波段低相噪频率合成器设计[J].无线电工程,2012,42(3):44-46.
[14]吴俊晨,任文成,徐志平.利用PLL减小时钟前沿抖动的研究[J].无线电工程,2013,43(2):52-54.
[15]杨强,李栋贤.毫米波卫星通信频段功率合成器的研究[J].无线电工程,2013,43(5):59-61.
[16]胡丽格.一种S波段宽带小步进频率合成器的设计与实现[J].无线电工程,2015,45(5):70-72.
[17]王战永.基于DDS+PLL一种快速跳频频率合成电路的设计与实现[J].移动通信,2014,38(24):57-61,66.