一种使用时间斜移整形技术的ΔΣ时间数字转换器
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摘要
本文提出了一种使用门控环形振荡器及时间斜移整形技术的2-0级联结构的ΔΣ型TDC.该TDC使用了一个环形DTC和基于时间寄存器的时域加法器,DTC通过与GRO-TDC共享量化器从而无需校准并且降低了功耗.通过将GRO量化器的输出分割为MSB和LSB部分,环形DTC的精度要求被进一步降低.利用该时间斜移整形技术,GRO的时间斜移误差被一阶整形,同时死区效应被解决.与此同时,实现了量化噪声的二阶整形.该项技术易于在宽带和低功耗方面得到应用.
A 2-0 cascade gated-ring-oscillator(GRO)basedΔΣtime-to-digital converter(TDC)using time-skew shaping technique is presented in this paper.The proposed TDC includes a ring digital-to-time converter(RingDTC)and a time-register(TR)based time-domain adder.By sharing the intrinsic gated-ring quantizer of GROTDC,the Ring-DTC has performed no additional matching requirement,calibration free and low power consumption.By dividing the outputs of the GRO quantizer into an MSB segment and an LSB segment,the resolution requirement of Ring-DTC is further released.With the proposed time skew shaping technique,the timeskew of GRO is 1 st order shaped,and the dead-zone effect is solved.At the same time,2 nd order quantization noise shaping is achieved.This technique is simple to implement and well suited for low-power and wide-band applications.
A 2-0 cascade gated-ring-oscillator(GRO)basedΔΣtime-to-digital converter(TDC)using time-skew shaping technique is presented in this paper.The proposed TDC includes a ring digital-to-time converter(RingDTC)and a time-register(TR)based time-domain adder.By sharing the intrinsic gated-ring quantizer of GROTDC,the Ring-DTC has performed no additional matching requirement,calibration free and low power consumption.By dividing the outputs of the GRO quantizer into an MSB segment and an LSB segment,the resolution requirement of Ring-DTC is further released.With the proposed time skew shaping technique,the timeskew of GRO is 1 st order shaped,and the dead-zone effect is solved.At the same time,2 nd order quantization noise shaping is achieved.This technique is simple to implement and well suited for low-power and wide-band applications.
引文
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[2]Straayer M Z,Perrott M H.A multi-path gated ring oscillator tdc with first-order noise shaping[J].Ieee Journal of Solid-State Circuits,2009,44(4):1089-1098.
[3]Yu W,Kim K,Cho S.A 148fS(rms)integrated noise4 MHz bandwidth second-order delta sigma time-todigital converter with gated switched-ring oscillator[J].Ieee T Circuits-I,2014,61(8):2281-2289.
[4]谢润,刁盛锡,林福江.一种使用增益校准技术的ΔΣ时间数字转换器[J].微电子学与计算机,2016,33(11):137-141.
[5]Lee C C,Alpman E,Weaver S,et al.A 66dB SNDR15MHz BW SAR assistedΔΣADC in 22nm tri-gate CMOS[C]∥proceedings of the VLSI Circuits(VLSIC),2013Symposium on.Kyoto,Japan,IEEE,2013.
[6]Yu W,Kim K,CHO S.A 0.22ps(rms)Integrated Noise 15 MHz bandwidth fourth-order delta sigma time-to-digital converter using time-domain error-feedback filter[J].Ieee Journal of Solid-State Circuits,2015,50(5):1251-1262.
[7]Konishi T,Okuno K,Izumi S,et al.A second-order all-digital tdc with low-jitter frequency shift oscillators and dynamic flipflops[J].Ieice T Electron,2013,E96c(4):546-552.