一种低相位噪声的UHF频段小数分频频率综合器
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摘要
提出并实现了一款采用相位噪声优化技术的特高频(UHF)频段小数分频频率综合器,其工作频率为0.8~1.6 GHz。采用死区消除技术减少了鉴频鉴相器和电荷泵的噪声对系统的影响。采用分布式变容管结构和二阶谐波滤除技术设计压控振荡器,使压控振荡器获得了更低的相位噪声。采用新型的陷波滤波技术设计Δ-Σ调制器,进一步降低带内相位噪声和系统的杂散。采用TSMC 180 nm CMOS工艺进行了流片验证。测试结果表明该频率综合器在0.01,1和10 MHz频偏处的最大相位噪声分别为-95,-127和-146 dBc/Hz,杂散抑制低于-81 dBc,而频率综合器芯片的功耗仅为20 mW,芯片面积为2.5 mm×1.1 mm。
An ultrahigh frequency( UHF) band fractional-N frequency synthesizer with phase noise optimization technique was proposed and implemented,with an operating frequency of 0. 8-1. 6 GHz.The dead-zone elimination technique was adopted to reduce the noise influence induced by the phase frequency detector and charge pump on the system. The distributed varactor structure and second-order harmonic filtering technique were adopted in the voltage-controlled oscillator to achieve lower phase noise.The new type of notch filtering technique was adopted in the Δ-Σ modulator to further mitigate the inband phase noise and system spurs. The synthesizer was fabricated and verified in TSMC 180 nm CMOS process. The test results show that the proposed synthesizer achieves a maximum phase noise of -95,-127 and-146 dBc/Hz at 0. 01,1 and 10 MHz offset,with the spurious suppression less than -81 dBc and the power dissipation of only 20 mW. The chip area is 2. 5 mm×1. 1 mm.
An ultrahigh frequency( UHF) band fractional-N frequency synthesizer with phase noise optimization technique was proposed and implemented,with an operating frequency of 0. 8-1. 6 GHz.The dead-zone elimination technique was adopted to reduce the noise influence induced by the phase frequency detector and charge pump on the system. The distributed varactor structure and second-order harmonic filtering technique were adopted in the voltage-controlled oscillator to achieve lower phase noise.The new type of notch filtering technique was adopted in the Δ-Σ modulator to further mitigate the inband phase noise and system spurs. The synthesizer was fabricated and verified in TSMC 180 nm CMOS process. The test results show that the proposed synthesizer achieves a maximum phase noise of -95,-127 and-146 dBc/Hz at 0. 01,1 and 10 MHz offset,with the spurious suppression less than -81 dBc and the power dissipation of only 20 mW. The chip area is 2. 5 mm×1. 1 mm.
引文
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[14]YU X B,HAN S Y,JIN Z M,et al.A class-C VCO basedΣ-Δfraction-N frequency synthesizer with AFC for802.11 ah applications[J].Journal of Semiconductors,2015,36(9):115-120.
[15]韦祚东,林敏,陈卓俊.一种UHF频段小数分频频率综合器设计与实现[J].半导体技术,2017,42(7):505-510.WEI Z D,LIN M,CHEN Z J.Design and implementation of an UHF-band fractional-N frequency synthesizer[J].Semiconductor Technology,2017,42(7):505-510(in Chinese).
[2]LIU X L,ZHANG L,ZHANG L,et al.A 3.45-4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications[C]∥Proceedings of the 57thInternational Midwest Symposium on Circuits and Systems.College Station,TX,USA,2014:749-752.
[3]WU T,HANUMOLU P K,MAYARAM K,et al.Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers[J].IEEE Journal of Solid-State Circuits,2009,44(2):427-435.
[4]MAI X D,MINH C H P.A low phase noise frequency synthesizer for GPS RF receiver[C]∥Proceedings of the4thInternational Conference on Electrical and Electronic Engineering.Ankara,Turkey,2017:300-303.
[5]TIC L,LIU Y H,LIN T H.A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit[C]∥Proceedings of the IEEE International Symposium on Circuits and Systems.Seattle,WA,USA,2008:1728-1731.
[6]RILEY T A D,FILIOL N M,DU Q H,et al.Techniques for in-band phase noise reduction inΔ-Σsynthesizers[J].IEEE Transactions on Circuits and System:II,2003,50(11):794-803.
[7]HAJIMIRI A,LEE T H.A general theory of phase noise in electrical oscillators[J].IEEE Journal of Solid-State Circuits,1998,33(2):179-194.
[8]MIRA J,DIVEL T,RAMET S,et al.Distributed MOS varactor biasing for VCO gain equalization in 0.13μm CMOS technology[C]∥Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium.Forth Worth,TX,USA,2004:131-134.
[9]HEGAZI E,SJOLAND H,ABIDI A A.A filtering technique to lower LC oscillator phase noise[J].IEEE Journal of Solid-State Circuits,2001,36(12):1921-1930.
[10]PAMARTI S,GALTON I.LSB dithering in MASH delta-sigma D/A converters[J].IEEE Transactions on Circuits and Systems:I,2007,54(4):779-790.
[11]金晶.CMOS射频频率综合器的研究设计与优化[D].上海:上海交通大学,2012:23-24.
[12]刘深渊,杨清渊.锁相回路[M].台中:沧海书局,2006:20-21.
[13]HUANGF Q,WU J H,JI X C,et al.A 1.78-3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider[J].Analog Integrated Circuits and Signal Processing,2012,72(1):97-109.
[14]YU X B,HAN S Y,JIN Z M,et al.A class-C VCO basedΣ-Δfraction-N frequency synthesizer with AFC for802.11 ah applications[J].Journal of Semiconductors,2015,36(9):115-120.
[15]韦祚东,林敏,陈卓俊.一种UHF频段小数分频频率综合器设计与实现[J].半导体技术,2017,42(7):505-510.WEI Z D,LIN M,CHEN Z J.Design and implementation of an UHF-band fractional-N frequency synthesizer[J].Semiconductor Technology,2017,42(7):505-510(in Chinese).