卫星通信系统CMOS分数分频频率综合器设计
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摘要
基于CMOS工艺,设计了一款可用于无线卫星通信系统的低相噪、低杂散、24 bit分数分频频率综合器。频率综合器内部集成LC压控振荡器(VCO),通过自动增益控制电路调整VCO输出频率,采用电荷泵偏移电流线性化技术及Δ-Σ调制器加抖动技术改善相位噪声和杂散性能。在整数模式和分数模式下,带内相位噪声分别为-106.2 dBc/Hz和-99.7 dBc/Hz。VCO的输出频率为1.68～2.08 GHz,10 MHz频偏处相位噪声为-147.88 dBc/Hz。鉴相杂散和分数杂散均低于-72 dBc,分数模式下均方根抖动为634 fs。锁相环底噪声因子和闪烁噪声因子分别为-218.4 dBc/Hz和-249.6 dBc/Hz。频率综合器功率为75 mW,版图面积为1.2 mm×0.8 mm。
A low phase noise, low spur and 24 bit fractional synthesizer for wireless satellite communications system was designed based on the CMOS process. The LC voltage-controlled oscillator(VCO) was integrated in the frequency synthesizer, and the output frequency of VCO was adjusted by the automatic gain control circuit. The charge pump current-offset linearization technique and Δ-Σ modulator dithering techniques were used to improve the phase noise and spur performance. In the integer mode and fraction mode the in-band phase noises are-106.2 dBc/Hz and-99.7 dBc/Hz, respectively. The output frequency range of VCO is from 1.68 GHz to 2.08 GHz and the phase noise is-147.88 dBc/Hz @10 MHz. The reference spur and fractional spur are lower than-72 dBc and the RMS jitter is 634 fs. The noise floor factor and the flicker noise factor of the puase lock loop are-218.4 dBc/Hz and-249.6 dBc/Hz, respectively. The power of frequency synthesizer is 75 mW and occupies 1.2 mm×0.8 mm.
A low phase noise, low spur and 24 bit fractional synthesizer for wireless satellite communications system was designed based on the CMOS process. The LC voltage-controlled oscillator(VCO) was integrated in the frequency synthesizer, and the output frequency of VCO was adjusted by the automatic gain control circuit. The charge pump current-offset linearization technique and Δ-Σ modulator dithering techniques were used to improve the phase noise and spur performance. In the integer mode and fraction mode the in-band phase noises are-106.2 dBc/Hz and-99.7 dBc/Hz, respectively. The output frequency range of VCO is from 1.68 GHz to 2.08 GHz and the phase noise is-147.88 dBc/Hz @10 MHz. The reference spur and fractional spur are lower than-72 dBc and the RMS jitter is 634 fs. The noise floor factor and the flicker noise factor of the puase lock loop are-218.4 dBc/Hz and-249.6 dBc/Hz, respectively. The power of frequency synthesizer is 75 mW and occupies 1.2 mm×0.8 mm.
引文
[1] LI A, CHAO Y, CHEN X, et al. A spur-and-phase-noise-filtering technique for inductor-less fractional-N injection-locked PLLs[J]. IEEE Journal of Solid-State Circuits, 2017, 52(8): 2128-2140.
[2] SANYAL A, YU X Y, ZHANG Y L, et al. Fractional-N PLL with multi-element fractional divider for noise reduction[J]. Electronics Letters, 2016, 52(10): 809-810.
[3] LEE Y S, SEONG T, YOO S, et al. A low jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique[J]. IEEE Journal of Solid-State Circuits, 2018, 53(4): 1192-1202.
[4] SHU K,EDGAR S S. CMOS PLL synthesizer: analysis and design[M].Boston:Springer, 2005: 37-45.
[5] HOSSEINI K, KENNEDY M P. Minimizing spurious tones in digital delta-sigma modulators[M].New York: Springer, 2011:121-130.
[6] LIN T H,TI C L, LIU Y H. Dynamic current-matching charge pump and gate-offset linearization technique for delta-sigma fractional-N PLLs[J]. IEEE Transactions on Circuits and Systems:Ⅰ, 2009, 56(5): 877-885.
[7] KIM S G,RHIM J, KWON D H, et al. A low-voltage pll with a supply-noise compensated feedforward ring VCO[J]. IEEE Transactions on Circuits and Systems:Ⅱ, 2016, 63(6):548-552.
[8] ZHU J H, NANDWANA R K, SHU G H, et al. A 0.002 1 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2017, 52(1): 8-20.
[2] SANYAL A, YU X Y, ZHANG Y L, et al. Fractional-N PLL with multi-element fractional divider for noise reduction[J]. Electronics Letters, 2016, 52(10): 809-810.
[3] LEE Y S, SEONG T, YOO S, et al. A low jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique[J]. IEEE Journal of Solid-State Circuits, 2018, 53(4): 1192-1202.
[4] SHU K,EDGAR S S. CMOS PLL synthesizer: analysis and design[M].Boston:Springer, 2005: 37-45.
[5] HOSSEINI K, KENNEDY M P. Minimizing spurious tones in digital delta-sigma modulators[M].New York: Springer, 2011:121-130.
[6] LIN T H,TI C L, LIU Y H. Dynamic current-matching charge pump and gate-offset linearization technique for delta-sigma fractional-N PLLs[J]. IEEE Transactions on Circuits and Systems:Ⅰ, 2009, 56(5): 877-885.
[7] KIM S G,RHIM J, KWON D H, et al. A low-voltage pll with a supply-noise compensated feedforward ring VCO[J]. IEEE Transactions on Circuits and Systems:Ⅱ, 2016, 63(6):548-552.
[8] ZHU J H, NANDWANA R K, SHU G H, et al. A 0.002 1 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2017, 52(1): 8-20.