基于三值神经网络和混沌搜索的数字电路串扰时滞故障测试生成算法（英文）
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摘要
提出了一种有效的串扰时滞故障测试生成算法,该算法使用了三值神经网络理论和混沌搜索方法。首先在电路的受害点处把电路分成两个部分,对第一部分,可以得到时滞时间表达式;对第二部分,使用混沌搜索和三值神经网络网络的方法把故障传播到输出端。最后,能够把故障传播到输出端且使时滞时间表达式取最大值的输入矢量就是串扰时滞故障的最优测试矢量。实验结果表明该算法能够容易地得到故障输入测试矢量,平均测试生成时间小于0. 25μs,故障覆盖率能够达到98. 2%。
A kind of efficient crosstalk delay faults test generation algorithm was put forward in this paper. The algorithm used three-value neural networks theory and chaotic searching method. First,the circuit was decomposed into two parts at suffer point. For the first part circuit,a delay time equation can be obtained. For the second part circuit,chaotic searching method and three-value neural networks theory were used and the fault can be propagated to the output. At last,the input vectors which could propagate the fault to the output of the second part circuit and make the delay time equation of the first part circuit be maximum are the best input vectors for the crosstalk delay fault. The results of experiment show that the algorithm can get input test vectors easily. The average test generation time is less than 0. 25 μs and the fault-coverage rate can obtain above 98. 2%.
A kind of efficient crosstalk delay faults test generation algorithm was put forward in this paper. The algorithm used three-value neural networks theory and chaotic searching method. First,the circuit was decomposed into two parts at suffer point. For the first part circuit,a delay time equation can be obtained. For the second part circuit,chaotic searching method and three-value neural networks theory were used and the fault can be propagated to the output. At last,the input vectors which could propagate the fault to the output of the second part circuit and make the delay time equation of the first part circuit be maximum are the best input vectors for the crosstalk delay fault. The results of experiment show that the algorithm can get input test vectors easily. The average test generation time is less than 0. 25 μs and the fault-coverage rate can obtain above 98. 2%.
引文
[1]S.T.ZACHARIAH,Y.CHANG,S.KUNDU,et al.On Modeling Crosstalk Faults[C]//Proceedings of the conference on Design,Automation and Test in Europe,2009:104-109.
[2]J.M.RABAEY,A.CHANDRAKASAN.Digital Integrated Circuits:A Design Perspective[C]//2nd Edition,Prentice Hall,2012:446-452.
[3]KUNAL P,GANESHPURE,SANDIP KUNDU.Automatic Test Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults[C]//2013EDAA,2010:256-258.
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[5]HIDEO FUJIWARA.Three-Value Neural Networks for Test Generation[C]//Proc.of 20th Fault-Tolerant Computing Symposium,1990:66-67.
[6]T.CHAKRDHAR,M.L.BUSHNELL,V.D.AGRAWAL.Toward Massively Parallel Automatic Test Generation[J].IEEETrans.Computer_Aided Design,1999,26(9):81-83.
[7]XUE Jianbin,LI Zhi.The Application of Neural Networks in the Simulation-based Test Generation Algorithm for Hybrid Circuits[J].Journal of Circuits and Systems,2001,6(4):109-110.
[8]JAVIER FERRER,PETER M.KRUSE.Search based algorithms for test sequence generation in functional Testing[J].Information and Software Technology,2014,7(14):4-10.
[9]LIU Xiaodong,SUN Shenghe.Neural networks based test generation algorithm for combinational logic circuits[J].Journal of Harbin institute of technology,2002,34(22):56-57.
[10]REZA NOURMANDI-POUR,NAFISEHMOUSAVIAN.Afully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC[J].Microelectronics Journal,2013,35(1):48-50.
[11]JIRI BALCAREK,PETR FISER,JAN SCHMIDT.Techniques for SAT-based constrained test pattern generation[J].Microprocessors and Microsystems,2001,39(10):185-189.
[12]WU Lihua,WANG Xudong.Three-valued neural network test generation algorithm for Multi-faults based on genetic optimization[J].Chinese Journa l of Scientific Instrument,2010,31(8):44-49.
[13]XU Jianbin,LI Zhi.The Application of Neural Networks in the Simulation-based Test Generation Algorithm for Hybrid Circuits[J].Journal of Circuits and Systems,2009,16(4):109-110.
[14]WANG Guangyi,YUAN Fang.Cascade Chaos and Its Dynamic Characteristics[J].Acta Physica Sinica,2013,62(2):8-10.
[2]J.M.RABAEY,A.CHANDRAKASAN.Digital Integrated Circuits:A Design Perspective[C]//2nd Edition,Prentice Hall,2012:446-452.
[3]KUNAL P,GANESHPURE,SANDIP KUNDU.Automatic Test Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults[C]//2013EDAA,2010:256-258.
[4]C.WERNER,R.GOTTSCHE.Crosstalk noise in future CMOS circuits[C]//DATA2001,2001:331-335.
[5]HIDEO FUJIWARA.Three-Value Neural Networks for Test Generation[C]//Proc.of 20th Fault-Tolerant Computing Symposium,1990:66-67.
[6]T.CHAKRDHAR,M.L.BUSHNELL,V.D.AGRAWAL.Toward Massively Parallel Automatic Test Generation[J].IEEETrans.Computer_Aided Design,1999,26(9):81-83.
[7]XUE Jianbin,LI Zhi.The Application of Neural Networks in the Simulation-based Test Generation Algorithm for Hybrid Circuits[J].Journal of Circuits and Systems,2001,6(4):109-110.
[8]JAVIER FERRER,PETER M.KRUSE.Search based algorithms for test sequence generation in functional Testing[J].Information and Software Technology,2014,7(14):4-10.
[9]LIU Xiaodong,SUN Shenghe.Neural networks based test generation algorithm for combinational logic circuits[J].Journal of Harbin institute of technology,2002,34(22):56-57.
[10]REZA NOURMANDI-POUR,NAFISEHMOUSAVIAN.Afully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC[J].Microelectronics Journal,2013,35(1):48-50.
[11]JIRI BALCAREK,PETR FISER,JAN SCHMIDT.Techniques for SAT-based constrained test pattern generation[J].Microprocessors and Microsystems,2001,39(10):185-189.
[12]WU Lihua,WANG Xudong.Three-valued neural network test generation algorithm for Multi-faults based on genetic optimization[J].Chinese Journa l of Scientific Instrument,2010,31(8):44-49.
[13]XU Jianbin,LI Zhi.The Application of Neural Networks in the Simulation-based Test Generation Algorithm for Hybrid Circuits[J].Journal of Circuits and Systems,2009,16(4):109-110.
[14]WANG Guangyi,YUAN Fang.Cascade Chaos and Its Dynamic Characteristics[J].Acta Physica Sinica,2013,62(2):8-10.