基于FPGA的全数字延时锁相环的设计
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摘要
针对传统模拟延时锁相环锁相精度不高、锁相速度慢、集成度低等问题,提出一种全数字延迟锁相环,采用电子设计自动化技术进行设计,并通过QuartusⅡ软件予以编辑与分析。仿真结果表明,该延时锁相环能够快速锁定,并能达到很高的精度,且可移植性强,适用于多种应用领域如微处理器、存储器与通用IC
In allusion to the problems such as low phase-locking accuracy,slow phase-locking speed and low integration level of the traditional analog delay-locked loop(DLL),an all-digital DLL is proposed. The DLL is designed by using the elec-tronic design automation technology. The editing and analysis of the DLL are conducted by using the Quartus Ⅱ software. The simulation results show that the DLL can perform quick lock with high precision,has strong portability,and is suitable for vari-ous application fields such as microprocessor,memory and general IC designs.
In allusion to the problems such as low phase-locking accuracy,slow phase-locking speed and low integration level of the traditional analog delay-locked loop(DLL),an all-digital DLL is proposed. The DLL is designed by using the elec-tronic design automation technology. The editing and analysis of the DLL are conducted by using the Quartus Ⅱ software. The simulation results show that the DLL can perform quick lock with high precision,has strong portability,and is suitable for vari-ous application fields such as microprocessor,memory and general IC designs.
引文
[1]张刚.CMOS集成锁相环电路设计[M].北京:清华大学出版社,2013.ZHANG Gang.Design of CMOS integrated phase-locked loops[M].Beijing:Tsinghua University Press,2013.
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[4]保慧琴,尹国福.快速锁定的全数字延迟锁相环研究[J].微处理机,2016,37(1):11-14.BAO Huiqin,YIN Guofu.A fast-locking all-digital delaylocked loop[J].Microprocessors,2016,37(1):11-14.
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[6]邱有刚,黄建国,李力.基于FPGA数字延迟单元的实现和比较[J].电子测量技术,2011,34(9):65-68.QIU Yougang,HUANG Jianguo,LI Li.The implementation and comparison of DDL based on FPGA[J].Electronic measurement technology,2011,34(9):65-68.
[7]BRANDONISIO F,KENNEDY M P.First order noise shaping in all digital PLLs[C]//Proceedings of IEEE International Symposium of Circuits and Systems.Rio de Janeiro:IEEE,2011:161-164.
[8]罗宁,陈原聪,赵野.应用于全数字锁相环的高性能数控振荡器设计[J].微电子学与计算机,2015,32(12):59-62.LUO Ning,CHEN Yuancong,ZHAO Ye.Design of high performance digitally controlled oscillator for all-digital phaselocked-loop application[J].Microelectronics&computer,2015,32(12):59-62.
[9]NGUYEN A T,JOSE S.Fast-locking DLL circuit and method with phased output clock:6501312B1[P].2002-12-31.
[10]赵雯,尹军舰,赵潇腾,等.PLLFS快速锁定方法的研究与设计[J].电子设计工程,2017,25(9):162-166.ZHAO Wen,YIN Junjian,ZHAO Xiaoteng,et al.Analysis and design of fast-lock methods for PLLFS[J].Electronic design engineering,2017,25(9):162-166.
[2]CHEN X,YANG J,SHI L.A fast locking all-digital phaselocked loop via feed-forward compensation technique[J].IEEEtransactions on very large scale integration systems,2011,19(5):857-868.
[3]FAISAL M,WENTZLOFF D D.An automatically placed-androuted ADPLL for the medradio band using PWM to enhance DCO resolution[C]//Proceedings of IEEE Radio Frequency Integrated Circuits Symposium.Seattle:IEEE,2013:115-118.
[4]保慧琴,尹国福.快速锁定的全数字延迟锁相环研究[J].微处理机,2016,37(1):11-14.BAO Huiqin,YIN Guofu.A fast-locking all-digital delaylocked loop[J].Microprocessors,2016,37(1):11-14.
[5]张健.基于数字DLL时钟发生器的设计[D].西安:西安电子科技大学,2013.ZHANG Jian.Design of digital DLL clock generator[D].Xi’an:Xidian University,2013.
[6]邱有刚,黄建国,李力.基于FPGA数字延迟单元的实现和比较[J].电子测量技术,2011,34(9):65-68.QIU Yougang,HUANG Jianguo,LI Li.The implementation and comparison of DDL based on FPGA[J].Electronic measurement technology,2011,34(9):65-68.
[7]BRANDONISIO F,KENNEDY M P.First order noise shaping in all digital PLLs[C]//Proceedings of IEEE International Symposium of Circuits and Systems.Rio de Janeiro:IEEE,2011:161-164.
[8]罗宁,陈原聪,赵野.应用于全数字锁相环的高性能数控振荡器设计[J].微电子学与计算机,2015,32(12):59-62.LUO Ning,CHEN Yuancong,ZHAO Ye.Design of high performance digitally controlled oscillator for all-digital phaselocked-loop application[J].Microelectronics&computer,2015,32(12):59-62.
[9]NGUYEN A T,JOSE S.Fast-locking DLL circuit and method with phased output clock:6501312B1[P].2002-12-31.
[10]赵雯,尹军舰,赵潇腾,等.PLLFS快速锁定方法的研究与设计[J].电子设计工程,2017,25(9):162-166.ZHAO Wen,YIN Junjian,ZHAO Xiaoteng,et al.Analysis and design of fast-lock methods for PLLFS[J].Electronic design engineering,2017,25(9):162-166.