三值T门组合网络自动综合的理论和算法
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摘要
利用具有补运算三值格代数系统和三值T代数系统的基本运算和主要性质,提出了基于三值逻辑函数简化不相交积之和形式的三值T门组合网络自动综合的一些理论问题和算法,并给出了应用实例.利用CMOS管电路实现了三值T门模块和应用实例中的三值T门组合网络.HSPICE仿真实验验证了所设计的三值T门组合网络逻辑功能正确,表明该算法是有效的.该方法易实现三值T门组合网络的自动综合.
In this paper,some theoretical analysis and an algorithm of automated synthesis of ternary T-gate combinational logic networks based on reduced disjoint sum-of-products forms of ternary logic functions are presented by using the fundamental operations and main properties of the ternary lattice algebra system with complement operation and ternary T-algebra system.An application example of the method is given.The ternary T-gate model and the ternary-gate combinational logic network in the application example are realized by using circuits of CMOS transistors.The correctness and the effectiveness of the logical function for the designed ternary T-gate combinational network is verified by the HSPICE simulation experiment.With this method,automated synthesis of ternary T-gate combinational logic networks can easily be accomplished on a computer.
In this paper,some theoretical analysis and an algorithm of automated synthesis of ternary T-gate combinational logic networks based on reduced disjoint sum-of-products forms of ternary logic functions are presented by using the fundamental operations and main properties of the ternary lattice algebra system with complement operation and ternary T-algebra system.An application example of the method is given.The ternary T-gate model and the ternary-gate combinational logic network in the application example are realized by using circuits of CMOS transistors.The correctness and the effectiveness of the logical function for the designed ternary T-gate combinational network is verified by the HSPICE simulation experiment.With this method,automated synthesis of ternary T-gate combinational logic networks can easily be accomplished on a computer.
引文
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[2]PAREL V,GURUMURTHY K S.Arithmetic operations in multi-valued logic[J].International Journal of VLSI design&Communication Systems,2010,1(1):21-32.
[3]TOTO F,SALETTI R.CMOS dynamic ternary circuit with full logic swing and zero-static power consumption[J].Electronic Letters,1998,34(11):1083-1084.
[4]LIN S,KIM Y B,LOMBARDI F.CNTFET-based design of ternary logic gates and arithmetic circuits[J].IEEE Transactions on Nanotechnology,2011,10(2):217-225.
[5]KESHAVARZIAN P,SARIKHANI R.A novel CNTFET-based ternary fall adder[J].Circuits Syst Signal Processing,2014,33(3):665-679.
[6]INOKAWA H,FUJIWARA A,TAKAHASHI Y.Amultiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors[J].IEEE Transactions on Electron Devices,2003,50(2):462-470.
[7]WAIRYA S,NAGARIA R K,TIWARI S.New design methodologies for high-speed mixed-mode CMOSfull adder circuits[J].International Journal of VLSIdesign&Communication Systems,2011,2(2):78-98.
[8]吴训威.多值逻辑电路设计原理[M].杭州:杭州大学出版社,1994.WU X W.Design Principles of Multi-Valued Logic Circuits[M].Hangzhou:Hangzhou University Press,1994.
[9]FANG K Y,WOJCIK A S.Modular decomposition of combinational multiple-valued circuits[J].IEEE Transactions on Computers,1988,37(10):1293-1301.
[10]姜恩华,姜文彬.三值逻辑函数RDSOP形式的代数理论和T门实现[J].计算机学报,2007,30(7):1132-1137.JIANG E H,JIANG W B.Algebra theory of RDSOPforms of ternary logic functions and its implementation with T-gates[J].Chinese Journal of Computers,2007,30(7):1132-1137.
[11]WANG Y,MCCROSKY C.Solving Boolean equations using ROSOP forms[J].IEEE Transactions on Computers,1998,47(2):171-177.