高k栅介质SOILDMOS管阈特性分析与建模
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摘要
通过分析高k栅介质SOI LDMOS管沟道与埋氧层的关系,建立了SOI LDMOS管的阈特性模型。研究了器件主要结构参数对阈特性及小尺寸效应的影响,分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系。通过软件ISE TCAD进行模拟仿真。结果表明,在不同的tSi和NA条件下,阈值电压的模型计算与数值模拟值吻合率为94.8%,最大差值为0.012 V,不同沟道长度SOI LDMOS的阈值电压漂移率为3.52%,最大漂移电压为0.008 V,模型计算值与数值模拟结果基本吻合。
Through the analysis of the relationship between high k gate dielectric SOI LDMOS trench and buried oxygen layer,threshold characteristics model of SOI LDMOS tube was established.The effect of device main structure parameters on the threshold characteristics and the small size effect were analyzed,the relationship of the threshold voltage and high k gate dielectric permittivity and the doping concentration of strain Si layer were analyzed.Simulation was conducted by using software ISE TCAD.Results show that under the condition of different tSi and NA,the self-agreement rate of model calculation and numerical simulation of threshold voltage is 94.8%,the biggest difference is 0.012 V,SOI LDMOS threshold voltage drift rate of different channel lengths is 3.52%,the maximum drift voltage is 0.008 V,model calculation values and numerical simulation results are basically in agreement.
Through the analysis of the relationship between high k gate dielectric SOI LDMOS trench and buried oxygen layer,threshold characteristics model of SOI LDMOS tube was established.The effect of device main structure parameters on the threshold characteristics and the small size effect were analyzed,the relationship of the threshold voltage and high k gate dielectric permittivity and the doping concentration of strain Si layer were analyzed.Simulation was conducted by using software ISE TCAD.Results show that under the condition of different tSi and NA,the self-agreement rate of model calculation and numerical simulation of threshold voltage is 94.8%,the biggest difference is 0.012 V,SOI LDMOS threshold voltage drift rate of different channel lengths is 3.52%,the maximum drift voltage is 0.008 V,model calculation values and numerical simulation results are basically in agreement.
引文
[1]FIORENZA J G,DEL A J.A experimental comparison of RF power LDMOSFETS on thin-film SOI and bulk silicon[J].IEEE Trans Electron Device,2002,49(4):687-692.
[2]CHENG X H,YANG W W,SONG Z R.A novel LDMOS structure in thin film patterned-SOI technology with a silicon window beneath p well[J].Chin J Semicond,2004,25(12):1580-1584.
[3]KINOSHITA K,TAKAHASHI H,FVIJII N.Recovery of plasma process induced damage in porous silica low k films by organosiloxane organosi coxame vapor post annealing[C]//2005 International Conference on Integrated Circuit Design and Technology(ICICDT).Pisa,Italy:IEEE,2005.
[4]EDELSTEIN D,DAVIS C,CLEVENGER L.Reliability,yield,and performance of a 90 nm SOI/Cu/Si COH technology[C]//Proceedings of International Interconnect Technology Conference.Boston,USA:IEEE,2004.
[5]陈晓娟,陈东阳,申雅茹.基于低频噪声测量的UPS故障诊断方法[J].电子器件,2015,38(2):1-5.
[6]JURCZAK M,SKOTNICKI T,PAOLI M.SON(silicon on nothing)-a new device architecture for the ULSI Era[C]//Symposium on VLSI Technology Digest of Technical Papers.Tokyo,Japan:The Conference Organizer,1999.
[7]赵洪利,曾传滨,刘魁勇,等.DCIV技术表征MOS/SOI界面陷阱能级密度分布[J].半导体技术,2015(1):63-67.
[8]杨文伟.SOI RESURF原理研究及SOI LDMOS研制[D].上海:中国科学院上海微系统所与信息技术研究所,2004.
[9]DEVASHISH P,LENKA T R.Model development for analyzing 2DEG sheet charge density and threshold voltage considering interface DOS for Al In N/Ga N MOSHEMT[J].J Semiconduct,2014,10:35-43.
[10]娄建忠,代鹏超,李曼,等.外延Ce O2高k栅介质层的结构及介电性能[J].电子元件与材料,2011,30(3):32-35.
[11]谭稀,蒲年年,徐冬梅,等.功率VDMOS器件漏电流、热阻与软焊料空洞率的关系[J].电子器件,2015(1):37-43.
[12]陈伟,方泽波,谌家军.非晶Er Al O高k栅介质薄膜的制备及性能研究[J].电子元件与材料,2010,29(1):28-31.
[2]CHENG X H,YANG W W,SONG Z R.A novel LDMOS structure in thin film patterned-SOI technology with a silicon window beneath p well[J].Chin J Semicond,2004,25(12):1580-1584.
[3]KINOSHITA K,TAKAHASHI H,FVIJII N.Recovery of plasma process induced damage in porous silica low k films by organosiloxane organosi coxame vapor post annealing[C]//2005 International Conference on Integrated Circuit Design and Technology(ICICDT).Pisa,Italy:IEEE,2005.
[4]EDELSTEIN D,DAVIS C,CLEVENGER L.Reliability,yield,and performance of a 90 nm SOI/Cu/Si COH technology[C]//Proceedings of International Interconnect Technology Conference.Boston,USA:IEEE,2004.
[5]陈晓娟,陈东阳,申雅茹.基于低频噪声测量的UPS故障诊断方法[J].电子器件,2015,38(2):1-5.
[6]JURCZAK M,SKOTNICKI T,PAOLI M.SON(silicon on nothing)-a new device architecture for the ULSI Era[C]//Symposium on VLSI Technology Digest of Technical Papers.Tokyo,Japan:The Conference Organizer,1999.
[7]赵洪利,曾传滨,刘魁勇,等.DCIV技术表征MOS/SOI界面陷阱能级密度分布[J].半导体技术,2015(1):63-67.
[8]杨文伟.SOI RESURF原理研究及SOI LDMOS研制[D].上海:中国科学院上海微系统所与信息技术研究所,2004.
[9]DEVASHISH P,LENKA T R.Model development for analyzing 2DEG sheet charge density and threshold voltage considering interface DOS for Al In N/Ga N MOSHEMT[J].J Semiconduct,2014,10:35-43.
[10]娄建忠,代鹏超,李曼,等.外延Ce O2高k栅介质层的结构及介电性能[J].电子元件与材料,2011,30(3):32-35.
[11]谭稀,蒲年年,徐冬梅,等.功率VDMOS器件漏电流、热阻与软焊料空洞率的关系[J].电子器件,2015(1):37-43.
[12]陈伟,方泽波,谌家军.非晶Er Al O高k栅介质薄膜的制备及性能研究[J].电子元件与材料,2010,29(1):28-31.