22 nm FDSOI器件的制备与背偏效应研究
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摘要
提出了一种基于后栅极工艺的22 nm全耗尽绝缘体上硅(FDSOI)器件的制备方法。基于电学测试结果,分析了器件的基本性能,研究了背栅偏压对器件性能的影响。结果表明,器件的开关电流比比较高、亚阈值摆幅较小,符合产业的一般标准。背栅偏压对长沟道和短沟道器件的阈值电压均有明显的影响。电路设计人员可以根据不同需求,选择工作在正向体偏置(FBB)模式或者反向体偏置(RBB)模式的器件。
Preparation of a 22 nm fully depleted silicon-on-insulator(FDSOI) device by gate-last process was described. According to the electrical test results, the performance of fabricated transistors was thoroughly characterized and the effect of back bias on the performance of devices was studied in detail. The results showed that the fabricated transistors had met the industrial standards, such as a high on-state current/off-state current ratio and a low subthreshold swing. A significant back bias dependence was found for threshold voltage, thus a wide range of threshold voltage could be extended because of the back bias for long channel and short channel devices. The circuit designer could flexibly select devices that worked in forward body bias(FBB) mode or reverse body bias(RBB) mode, depending on the requirements.
Preparation of a 22 nm fully depleted silicon-on-insulator(FDSOI) device by gate-last process was described. According to the electrical test results, the performance of fabricated transistors was thoroughly characterized and the effect of back bias on the performance of devices was studied in detail. The results showed that the fabricated transistors had met the industrial standards, such as a high on-state current/off-state current ratio and a low subthreshold swing. A significant back bias dependence was found for threshold voltage, thus a wide range of threshold voltage could be extended because of the back bias for long channel and short channel devices. The circuit designer could flexibly select devices that worked in forward body bias(FBB) mode or reverse body bias(RBB) mode, depending on the requirements.
引文
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[10] NOEL J P,THOMAS O,JAUD M A,et al.Multi-VT UTBB FDSOI device architectures for low-power CMOS circuit [J].IEEE Trans Elec Dev,2011,58(8):2473-2482.
[11] OHTA H,KIM Y,SHIMAMUNE Y,et al.High performance 30 nm gate bulk CMOS for 45 nm node with Σ-shaped SiGe-SD [C] // IEDM.Washington D C,USA.2005:237-240.
[2] SKOTNICKI T,MONFRAY S.UTBB FDSOI:evolution and opportunities [J].Sol Sta Elec,2016,125(11):63-72.
[3] DORIS B,DESALVO B,CHENG K,et al.Planar fully - depleted - silicon - on - insulator technologies:toward the 28 nm node and beyond [J].Sol Sta Elec,2016,117(3):37-59.
[4] TRIYOSO D H,CARTER R,KLUTH J,et al.Extending HKMG scaling on CMOS with FDSOI:advantages and integration challenges [C] // IEEE Int Conf IC Des & Technol.Hochiminh,Vietnam.2016:1-4.
[5] ANDRIEU F,FAYNOT O,GARROS X,et al.Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI cMOSFETs down to 25 nm gate length and width [C] // IEDM.San Francisco,CA,USA.2006:1-4.
[6] WIDIEZ J,VINET M,POIROUX T,et al.TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties [C]// IEEE Int SOI Conf Proceed.Honolulu,HI,USA.2005:30-31.
[7] VELOSO A,RAGNARSSON L,CHO M J,et al.Gate-last vs.gate-first technology for aggressively scaled EOT logic/RF CMOS [C] // IEEE Symp VLSI Technol.Honolulu,HI,USA.2011:34-35.
[8] AUTH C,CAPPELLANI A,CHUN J S,et al.45 nm high-k+ metal gate strain-enhanced transistors [C] // IEEE Symp VLSI Technol.Honolulu,HI,USA.2008:128-129.
[9] MORVAN S,ROYER C L,ANDRIEU F,et al.Gate-last integration on planar FDSOI MOSFET:impact of mechanical boosters and channel orientations [C] // IEDM.Washington D C,USA.2013:20.3.1-20.3.4.
[10] NOEL J P,THOMAS O,JAUD M A,et al.Multi-VT UTBB FDSOI device architectures for low-power CMOS circuit [J].IEEE Trans Elec Dev,2011,58(8):2473-2482.
[11] OHTA H,KIM Y,SHIMAMUNE Y,et al.High performance 30 nm gate bulk CMOS for 45 nm node with Σ-shaped SiGe-SD [C] // IEDM.Washington D C,USA.2005:237-240.