高效低复杂度的QC-LDPC码全并行分层结构译码器
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摘要
针对传统的部分并行结构低密度奇偶校验码(low-density parity-check codes,LDPC)译码器在保证较高吞吐量的同时,存在消耗硬件资源较大、迭代译码收敛速度较慢等问题,提出一种高效低复杂度的准循环低密度奇偶校验(quasi-cyclic low-density parity-check,QC-LDPC)码全并行分层结构译码器。这种改进的译码器结构可有效降低存储资源消耗,并克服并行处理所导致的访问冲突等问题。设计中,后验概率信息和信道初始化信息共用一个存储模块,降低了一半存储空间的占用。各个分层之间采用相对偏移的方式,实现了分层的全并行更新,提高了译码吞吐量。分层最小和译码算法(layered min-sum decoding algorithm,LMSDA)加速了译码迭代的收敛,进一步提高了吞吐量。经ISE 14.2软件仿真及Virtex7系列开发板验证的结果表明,当译码器工作频率为302.7 MHz、迭代次数为10的情况下,吞吐量可达473.2 Mbit/s,存储资源消耗仅为传统部分并行结构译码器的1/4。
Aiming at the problem of too much hardware costs and slow convergence rates in traditional partial-parallel lowdensity parity-check(LDPC) decoders with high throughput,a full-parallel-layered decoder for quasi-cyclic low-density parity-check(QC-LDPC) codes with high efficiency and low complexity is proposed. The improved architecture of decoder can effectively reduce the memory resource consumption and overcome the problem of access conflict caused by the parallel processing. In this design,the posterior probability information and the channel initialization information share the same storage module,which reduce half of the storage space. The relative offset among the various layers is used for the full-parallel-layered updating,which promotes the throughput. Moreover,the layered min-sum decoding algorithm(LMSDA) accelerates the convergence of decoding iterations and further improves the throughput. By simulations on ISE 14.2 and validations on Virtex 7 series board,it has been shown that the proposed decoder can achieve a throughput up to 473.2 Mbit/s when working on 302.7 MHz with 10 iterations. Moreover,the consumable memory resource accounts for only 1/4 of the traditional decoder.
Aiming at the problem of too much hardware costs and slow convergence rates in traditional partial-parallel lowdensity parity-check(LDPC) decoders with high throughput,a full-parallel-layered decoder for quasi-cyclic low-density parity-check(QC-LDPC) codes with high efficiency and low complexity is proposed. The improved architecture of decoder can effectively reduce the memory resource consumption and overcome the problem of access conflict caused by the parallel processing. In this design,the posterior probability information and the channel initialization information share the same storage module,which reduce half of the storage space. The relative offset among the various layers is used for the full-parallel-layered updating,which promotes the throughput. Moreover,the layered min-sum decoding algorithm(LMSDA) accelerates the convergence of decoding iterations and further improves the throughput. By simulations on ISE 14.2 and validations on Virtex 7 series board,it has been shown that the proposed decoder can achieve a throughput up to 473.2 Mbit/s when working on 302.7 MHz with 10 iterations. Moreover,the consumable memory resource accounts for only 1/4 of the traditional decoder.
引文
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[15]SWAPNIL M,DAVID U,HOJEE K,et al.HighThroughput FPGA-based QC-LDPC Decoder Architecture[C]∥Vehicular Technology Conference.Boston,MA,USA:IEEE Press,2015:1-5.
[2]ZHANG Kai,HUANG Xinming,WANG Zhongfeng.An area-efficient LDPC decoder architecture and implementation for CMMB systems[C]∥2009 20th IEEE International Conference on Application-specific Systems,Architectures and Processors.Boston:IEEE Press,2009:235-238.
[3]MANSOUR M M.A turbo-decoding message-passing algorithm for sparse parity-check matrix codes[J].IEEE Transactions on Signal Processing,2006,54(11):4376-4392.
[4]MANSOUR M M,SHANBHAG N R.High-Thoughput LDPC Decoders[J].IEEE Transactions on Very Large Scale Integration Systems,2003,11(6):976-996.
[5]LIAO Ruochen,FU Yuzhuo,LIU Ting.FPGA-Based High Throughput TDMP LDPC Decoder[J].Computer Engineering and Technology,2016(666):94-101.
[6]YANG Lei,SHEN Manyuan,LIU Hui,et al.An FPGA implementation of low-density parity-check code decoder with multi-rate capability[C]∥Proceedings of the ASPDAC 2005.Asia and South Pacific Design Automation Conference,2005.Shanghai:IEEE Press,2005:760-763.
[7]袁瑞佳,白宝明.基于FPGA的LDPC码编译码器联合设计[J].电子与信息学报,2012,34(1):38-44.YUAN Ruijia,BAI Baoming.FPGA-based Joint Design of LDPC Encoder and Decoder[J].Journal of Electrics&Information Technology,2012,34(1):38-44.
[8]姚远.基于并行分层译码算法的LDPC译码器设计[D].上海:复旦大学,2013.YAO Yuan.Design of LDPC Decoder Based on Parallel Layered Decoding Algorithm[D].Shanghai:Fudan University,2013.
[9]周健,吕毅博,洪少华,等.面向磁记录信道的原模图LDPC码译码器的FPGA设计[J].重庆邮电大学学报:自然科学版,2013,25(6):788-794.ZHOU Jian,LV Yibo,HONG Shaohua,et al.Protographbased LDPC Decoder Applied to Magnetic Recording Channel[J].Journal of Chongqing University of Posts and Telecommunications:Natural Science Edition,2013,25(6):788-794.
[10]张顺根,仰枫帆.基于FPGA的随机构造QC-LDPC分层译码器设计[J].无线电通信技术,2015,41(1):41-45.ZHANG Shungen,YANG Fengfan.Design on Randomly Constructed QC-LDPC Layered Decoder Based on FPGA[J].Radio Communications Technology,2015,41(1):41-45.
[11]ZHANG Kai,HUANG Xinming,WANG Zhongfeng.High-throughput layered decoder implementation for quasi-cyclic LDPC codes[J].IEEE Journal on Selected Areas in Communications,2009,27(6):985-994.
[12]彭阳阳,仰枫帆.基于FPGA的QC-LDPC码分层译码器设计[J].无线电工程,2014,44(1):17-20.PENG Yangyang,YANG Fengfan.Design on QC-LDPC Layered Decoder Based on FPGA[J].Radio Engineering,2014,44(1):17-20.
[13]DING Hong,YANG Shuai,LUO Wu,et al.Design and implementation for high speed LDPC decoder with layered decoding[C]∥International Conference on Communications and Mobile Computing.Kunming:IEEE Press,2009:156-160.
[14]云飞龙,杜锋,朱宏鹏,等.一种高吞吐量QC-LDPC码译码器的FPGA实现[C]∥第七届中国卫星导航学术年会论文集.长沙:中国卫星导航学术年会,2016.YUN Feilong,DU Feng,ZHU Hongpeng,et al.FPGA Implementation of a High-throughput QC-LDPC[C]∥The Seventh China Satellite Navigation Academic Annual Proceedings.Changsha,China:The Seventh Annual Meeting of China Satellite Navigation,2016.
[15]SWAPNIL M,DAVID U,HOJEE K,et al.HighThroughput FPGA-based QC-LDPC Decoder Architecture[C]∥Vehicular Technology Conference.Boston,MA,USA:IEEE Press,2015:1-5.