快速锁定的全数字延迟锁相环研究
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摘要
为了消除芯片内部各模块间的时钟延时,减小时钟相位偏移,设计了一种快速锁定的全数字延迟锁相环结构,只需一次调节过程即可完成输入输出时钟的同步,锁定时间短,噪声不会积累,抗干扰性好。在监测相位差时利用一种新的相位选择方法,配合相应的控制逻辑电路,完成DLL的快速锁定,通过调整延迟单元的延时、个数及相应控制电路的大小,实现宽范围的相位锁定。SMIC 0.18μm CMOS工艺下的仿真结果表明,本设计能够在18个周期内完成输入时钟和输出时钟的相位同步,锁定范围是25MHz~300MHz,最大时间抖动为35ps。
In order to eliminate the clock delay among the different modules on a chip and reduce the phase shift of the clock,a new structure of a fast- locking all- digital delay- locked loop is presented in this paper,which can complete input and output clock synchronization with only once adjustment.Utilizing a new method of phase selector when detecting the phase difference to achieve the fast locking of DLL,by adjusting the delay of delay units,the number of delay units and the size of the corresponding control circuit,a wide range of phase- locking can be obtained. The simulation results in the SMIC0. 18μm CMOS technology show that this design can complete the phase synchronization of input clock and output clock within 18 cycles,with the locking frequency range of 25 MHz ~ 300 MHz and the peak-to- peak jitter of 35 ps.
In order to eliminate the clock delay among the different modules on a chip and reduce the phase shift of the clock,a new structure of a fast- locking all- digital delay- locked loop is presented in this paper,which can complete input and output clock synchronization with only once adjustment.Utilizing a new method of phase selector when detecting the phase difference to achieve the fast locking of DLL,by adjusting the delay of delay units,the number of delay units and the size of the corresponding control circuit,a wide range of phase- locking can be obtained. The simulation results in the SMIC0. 18μm CMOS technology show that this design can complete the phase synchronization of input clock and output clock within 18 cycles,with the locking frequency range of 25 MHz ~ 300 MHz and the peak-to- peak jitter of 35 ps.
引文
[1]You-Jen Wang,Shao-Ku Kao.All-Digital DelayLocked Loop/Pulsewidth-Control Loop with Adjustable Duty Cycles[J].IEEE Journal of Solid-state circuits,2006,41(6):653-712.
[2]G K Dehng,J M Hsu,C Y Yang.Clock-deskew buffer using a SAR-controlled delay-locked loop[J].IEEE J.Solid-State Circuits,2000,35(8):1128-1136.
[3]J S Wang,Y M Wang,C H Chen.An ultra-low-power fast-lock-in small-jitter all-digital DLL[J].IEEE Int.Solid-State Circuit Conf,2005,41(6):422-423.
[4]T Hamamoto,K Furutani,T Kubo.A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM[J].IEEE J.Solid-State Circuits,2004,39(6):194-206.
[5]S Kao,S I Liu.All-digital clock deskew buffer with variable duty cycle[J].IEICE Trans.Electron,2006,40(6):753-760.
[6]J.-T.Kwak,C.-K.Kwon,K.-W.Kim.Low cost high performance register-controlled digital DLL for 1Gbps_32DDR SDRAM[J].in Symp.VLSI Circuits Dig.Tech.Papers,2003,40(5):283-284.
[7]Shao-Ku Kao,Bo-Jiun Chen,Shen-Iuan Liu.A62.5-625-MHz Anti-Reset All-Digital DelayLocked Loop[J].IEEE Transactions on circuits and systems,2007,54(7):182-204.
[8]Yi-Ming Wang,Jinn-Shyan Wang.An all-digital50%duty-cycle corrector[J].IEEE International Symposium on Circuits and Systems,2004,2(3):925-928.
[2]G K Dehng,J M Hsu,C Y Yang.Clock-deskew buffer using a SAR-controlled delay-locked loop[J].IEEE J.Solid-State Circuits,2000,35(8):1128-1136.
[3]J S Wang,Y M Wang,C H Chen.An ultra-low-power fast-lock-in small-jitter all-digital DLL[J].IEEE Int.Solid-State Circuit Conf,2005,41(6):422-423.
[4]T Hamamoto,K Furutani,T Kubo.A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM[J].IEEE J.Solid-State Circuits,2004,39(6):194-206.
[5]S Kao,S I Liu.All-digital clock deskew buffer with variable duty cycle[J].IEICE Trans.Electron,2006,40(6):753-760.
[6]J.-T.Kwak,C.-K.Kwon,K.-W.Kim.Low cost high performance register-controlled digital DLL for 1Gbps_32DDR SDRAM[J].in Symp.VLSI Circuits Dig.Tech.Papers,2003,40(5):283-284.
[7]Shao-Ku Kao,Bo-Jiun Chen,Shen-Iuan Liu.A62.5-625-MHz Anti-Reset All-Digital DelayLocked Loop[J].IEEE Transactions on circuits and systems,2007,54(7):182-204.
[8]Yi-Ming Wang,Jinn-Shyan Wang.An all-digital50%duty-cycle corrector[J].IEEE International Symposium on Circuits and Systems,2004,2(3):925-928.