合理运用SI技术快速收敛高速数字电路设计
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摘要
随着数字电路集成度和工作频率的不断提高,信号完整性(Signal Integrity, SI)问题在产品研制过程中越来越突出。以惯导系统中的某导航计算机为例,针对故障信号回路,使用仿真软件对其SDRAM时钟信号进行信号完整性仿真,并进行优化设计。通过对比优化前和优化后的仿真与测量结果,验证了由于端接参数不匹配造成SDRAM时钟信号的非单调性畸变问题。仿真与测量结果表明,在产品研制流程中加入信号完整性仿真环节有利于设计快速收敛,提前规避风险,缩短研发周期,降低设计成本,提高电路产品的可靠性和电磁兼容性。
With the continuous improvement of the integration level and operating frequency of the digital circuits, the problem of signal integrity(SI) is becoming more and more prominent in product developing. Aiming at the fault signal loop, the signal integrity of SDRAM clock signal of a navigation computer in inertial navigation system is simulated by using simulation software, and the PCB is optimized. By comparing the simulation and measurement results before and after optimization, the nonmonotonic distortion of SDRAM clock signal due to the mismatch of end connection parameters is verified. The simulation and test results show that the simulation of signal integrity in product developing is benefit to accelerating the convergence of design, avoiding the risk in advance, shortening the development cycle, reducing the designing cost and improving the reliability and electromagnetic compatibility of circuit products.
With the continuous improvement of the integration level and operating frequency of the digital circuits, the problem of signal integrity(SI) is becoming more and more prominent in product developing. Aiming at the fault signal loop, the signal integrity of SDRAM clock signal of a navigation computer in inertial navigation system is simulated by using simulation software, and the PCB is optimized. By comparing the simulation and measurement results before and after optimization, the nonmonotonic distortion of SDRAM clock signal due to the mismatch of end connection parameters is verified. The simulation and test results show that the simulation of signal integrity in product developing is benefit to accelerating the convergence of design, avoiding the risk in advance, shortening the development cycle, reducing the designing cost and improving the reliability and electromagnetic compatibility of circuit products.
引文
[1] 周忠山. DDR2高速PCB设计与信号完整性[J]. 电子技术与软件工程, 2017(9):81. Zhou Zhongshan. DDR2 high speed PCB design and signal integrity[J]. Electronic Technology & Software Engineering, 2017(9):81(in Chinese).
[2] 谢锐, 裴东兴, 姚琴琴. 高频信号动态测试中的信号完整性分析[J]. 仪器仪表学报, 2017, 38(3):773-779. Xie Rui, Pei Dongxing, Yao Qinqin. Signal integrity analysis in high-frequency signal dynamic test[J]. Chinese Journal of Scientific Instrument, 2017, 38(3):773-779(in Chinese).
[3] 吴金玲. 基于DSP技术的导航计算机数据处理系统研究[J]. 电子设计工程, 2018, 26(7):59-62. Wu Jinling. Research on navigation computer data processing system based on DSP technology[J]. Electronic Design Engineering, 2018, 26(7):59-62(in Chinese).
[4] 缑丽敏, 刘陶, 刘良勇. 基于DSP和FPGA技术的导航计算机设计与实现[J]. 电脑知识与技术, 2017, 13(2):218-219. Gou Limin, Liu Tao, Liu Liangyong. Design and implementation of navigation computer based on DSP and FPGA technology[J]. Computer Knowledge and Technology, 2017, 13(2):218-219(in Chinese).
[5] 赵振涌,袁寰.高精度A/D转换技术在惯导系统中的应用研究[J].导航定位与授时, 2014,1(2): 70-73. Zhao Zhenyong, Yuan Huan. Research on high accuracy analog-to-digital convert for inertial navigation systems[J]. Navigation Positioning and Timing, 2014,1(2): 70-73(in Chinese).
[6] 刘旭东. DSP技术下导航计算机数据处理系统设计与实现[J]. 山东工业技术, 2017(16):169. Liu Xudong. Design and implementation of navigation computer data processing system based on DSP technology[J]. Shandong Industrial Technology, 2017(16):169(in Chinese).
[7] Wu Jinling. Research on navigation computer data processing system based on DSP technology[J]. Electronic Design Engineering, 2018.
[8] 张敏.高速并行总线接口信号的完整性及设计优化[J].无线互联科技,2018,15(6):3-4. Zhang Min. Signal integrity and design optimization of high speed parallel bus interface[J]. Wireless Internet Technology,2018,15(6):3-4(in Chinese).
[9] 陈治洲, 曹开钦, 柴孟阳, 等. 基于SRAM乒乓缓存信号完整性分析[J]. 现代电子技术, 2018, 41(5): 83-88. Chen Zhizhou, Cao Kaiqin, Chai Mengyang, et al. Signal integrity analysis based on ping-pong buffer circuit of SRAM[J]. Modern Electronics Technique, 2018, 41(5): 83-88(in Chinese).
[10] 肖成. 双DSP为核心导航计算机的模块化设计[J]. 菏泽学院学报, 2017, 39(5):50-54. Xiao Cheng. On modular design of navigation computer with double DSP[J]. Journal of Heze University, 2017, 39(5):50-54(in Chinese).
[11] 朱园园. 高速电路设计中的信号完整性研究[J]. 电子技术与软件工程, 2015(20):36. Zhu Yuanyuan. Signal integrity research in high speed circuit design[J]. Electronic Technology & Software Engineering, 2015(20):36(in Chinese).
[12] 金帅, 韩连刚, 谢锡海. DDR3与FPGA接口的高速电路板信号完整性分析[J]. 现代电子技术, 2017, 40(22):10-13. Jin Shuai, Han Liangang, Xie Xihai. Signal integrity analysis of high-speed circuit board interconnecting DDR3 and FPGA[J]. Modern Electronics Technique, 2017, 40(22):10-13(in Chinese).
[13] Lu T, Sun J, Wu K, et al. High-speed channel modeling with machine learning methods for signal integrity analysis[J]. IEEE Transactions on Electromagnetic Compatibility, 2018(99):1-8.
[14] 邓素辉, 谭子诚, 鄢秋荣, 等. 基于Cadence软件高速PCB设计的信号完整性仿真[J]. 实验室研究与探索, 2017(12):116-120. Deng Suhui, Tan Zicheng, Yan Qiurong, et al. Signal integrity simulation in the design of the high speed PCB by using Cadence software[J]. Research and Exploration in Laboratory, 2017(12):116-120(in Chinese).
[15] 王圣俊, 柴小丽, 颜爱良. 双存储控制系统中高速信号完整性设计[J]. 电子设计工程, 2018, 26(4):114-121. Wang Shengjun, Chai Xiaoli, Yan Ailiang. High-speed signal integrity design in gual storage control system[J]. Electronic Design Engineering, 2018, 26(4):114-121(in Chinese).
[16] 缑新科, 王妮儿, 任崇玉. PCB参数对LPDDR3信号完整性的影响[J]. 兰州理工大学学报, 2017, 43(2): 92-96. Gou Xinke, Wang Nier, Ren Chongyu. Influence of PCB parameters signal integrity of LPDDR3[J]. Journal of Lanzhou University of Technology, 2017, 43(2): 92-96(in Chinese).
[17] 周路, 贾宝富. 信号上升或下降时间对高速电路信号完整性影响的研究[J]. 现代电子技术, 2011, 34(6): 69-73. Zhou Lu, Jia Baofu. Effects of signal rise or fall time on high-speed circuits signal integrity[J]. Modern Electronics Technique, 2011, 34(6): 69-73(in Chinese).
[18] Wang S, Xu X, Zhou G, et al. Effects of microstrip line fabrication and design on high-speed signal integrity transmission of PCB manufacturing process[J]. Circuit World, 2018, 44(2): 53-59.
[2] 谢锐, 裴东兴, 姚琴琴. 高频信号动态测试中的信号完整性分析[J]. 仪器仪表学报, 2017, 38(3):773-779. Xie Rui, Pei Dongxing, Yao Qinqin. Signal integrity analysis in high-frequency signal dynamic test[J]. Chinese Journal of Scientific Instrument, 2017, 38(3):773-779(in Chinese).
[3] 吴金玲. 基于DSP技术的导航计算机数据处理系统研究[J]. 电子设计工程, 2018, 26(7):59-62. Wu Jinling. Research on navigation computer data processing system based on DSP technology[J]. Electronic Design Engineering, 2018, 26(7):59-62(in Chinese).
[4] 缑丽敏, 刘陶, 刘良勇. 基于DSP和FPGA技术的导航计算机设计与实现[J]. 电脑知识与技术, 2017, 13(2):218-219. Gou Limin, Liu Tao, Liu Liangyong. Design and implementation of navigation computer based on DSP and FPGA technology[J]. Computer Knowledge and Technology, 2017, 13(2):218-219(in Chinese).
[5] 赵振涌,袁寰.高精度A/D转换技术在惯导系统中的应用研究[J].导航定位与授时, 2014,1(2): 70-73. Zhao Zhenyong, Yuan Huan. Research on high accuracy analog-to-digital convert for inertial navigation systems[J]. Navigation Positioning and Timing, 2014,1(2): 70-73(in Chinese).
[6] 刘旭东. DSP技术下导航计算机数据处理系统设计与实现[J]. 山东工业技术, 2017(16):169. Liu Xudong. Design and implementation of navigation computer data processing system based on DSP technology[J]. Shandong Industrial Technology, 2017(16):169(in Chinese).
[7] Wu Jinling. Research on navigation computer data processing system based on DSP technology[J]. Electronic Design Engineering, 2018.
[8] 张敏.高速并行总线接口信号的完整性及设计优化[J].无线互联科技,2018,15(6):3-4. Zhang Min. Signal integrity and design optimization of high speed parallel bus interface[J]. Wireless Internet Technology,2018,15(6):3-4(in Chinese).
[9] 陈治洲, 曹开钦, 柴孟阳, 等. 基于SRAM乒乓缓存信号完整性分析[J]. 现代电子技术, 2018, 41(5): 83-88. Chen Zhizhou, Cao Kaiqin, Chai Mengyang, et al. Signal integrity analysis based on ping-pong buffer circuit of SRAM[J]. Modern Electronics Technique, 2018, 41(5): 83-88(in Chinese).
[10] 肖成. 双DSP为核心导航计算机的模块化设计[J]. 菏泽学院学报, 2017, 39(5):50-54. Xiao Cheng. On modular design of navigation computer with double DSP[J]. Journal of Heze University, 2017, 39(5):50-54(in Chinese).
[11] 朱园园. 高速电路设计中的信号完整性研究[J]. 电子技术与软件工程, 2015(20):36. Zhu Yuanyuan. Signal integrity research in high speed circuit design[J]. Electronic Technology & Software Engineering, 2015(20):36(in Chinese).
[12] 金帅, 韩连刚, 谢锡海. DDR3与FPGA接口的高速电路板信号完整性分析[J]. 现代电子技术, 2017, 40(22):10-13. Jin Shuai, Han Liangang, Xie Xihai. Signal integrity analysis of high-speed circuit board interconnecting DDR3 and FPGA[J]. Modern Electronics Technique, 2017, 40(22):10-13(in Chinese).
[13] Lu T, Sun J, Wu K, et al. High-speed channel modeling with machine learning methods for signal integrity analysis[J]. IEEE Transactions on Electromagnetic Compatibility, 2018(99):1-8.
[14] 邓素辉, 谭子诚, 鄢秋荣, 等. 基于Cadence软件高速PCB设计的信号完整性仿真[J]. 实验室研究与探索, 2017(12):116-120. Deng Suhui, Tan Zicheng, Yan Qiurong, et al. Signal integrity simulation in the design of the high speed PCB by using Cadence software[J]. Research and Exploration in Laboratory, 2017(12):116-120(in Chinese).
[15] 王圣俊, 柴小丽, 颜爱良. 双存储控制系统中高速信号完整性设计[J]. 电子设计工程, 2018, 26(4):114-121. Wang Shengjun, Chai Xiaoli, Yan Ailiang. High-speed signal integrity design in gual storage control system[J]. Electronic Design Engineering, 2018, 26(4):114-121(in Chinese).
[16] 缑新科, 王妮儿, 任崇玉. PCB参数对LPDDR3信号完整性的影响[J]. 兰州理工大学学报, 2017, 43(2): 92-96. Gou Xinke, Wang Nier, Ren Chongyu. Influence of PCB parameters signal integrity of LPDDR3[J]. Journal of Lanzhou University of Technology, 2017, 43(2): 92-96(in Chinese).
[17] 周路, 贾宝富. 信号上升或下降时间对高速电路信号完整性影响的研究[J]. 现代电子技术, 2011, 34(6): 69-73. Zhou Lu, Jia Baofu. Effects of signal rise or fall time on high-speed circuits signal integrity[J]. Modern Electronics Technique, 2011, 34(6): 69-73(in Chinese).
[18] Wang S, Xu X, Zhou G, et al. Effects of microstrip line fabrication and design on high-speed signal integrity transmission of PCB manufacturing process[J]. Circuit World, 2018, 44(2): 53-59.