一种基于CUDA的截断重叠维特比译码算法
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摘要
为解决信道译码在高吞吐量通信系统中的瓶颈问题,通过对CUDA并行计算的了解和对维特比译码并行实现的探索,为卷积码提出了一种基于CUDA的截断重叠维特比译码器。算法通过截断式的子网格图相互重叠的方式,并行执行独立的正向度量计算和回溯过程。实验结果表明,在保证了译码算法误码率性能的同时,获得了良好的吞吐量提升表现,相比现有的实现方式提升了1. 3～3. 5倍,降低了硬件开销,能够有效运用于实际高吞吐量通信系统中。
In order to solve the bottleneck problem of channel decoding in high-throughput communication systems,this paper proposed a truncated overlap Viterbi decoder based on CUDA for convolutional codes to solve it by analyzing of parallel processing based on compute unified device architecture( CUDA) and exploring of the parallel implementation of Viterbi decoding. The algorithm performed both independent forward metrics computing and back-track procedure in parallel through the overlapping of truncated sub-grid. The experiment shows that the method keeps low BER,achieves a performance improvement of 1. 3 ～ 3. 5 times of the existing implementation and reduces hardware consumption. It can be effectively used in practical high-throughput communication systems.
In order to solve the bottleneck problem of channel decoding in high-throughput communication systems,this paper proposed a truncated overlap Viterbi decoder based on CUDA for convolutional codes to solve it by analyzing of parallel processing based on compute unified device architecture( CUDA) and exploring of the parallel implementation of Viterbi decoding. The algorithm performed both independent forward metrics computing and back-track procedure in parallel through the overlapping of truncated sub-grid. The experiment shows that the method keeps low BER,achieves a performance improvement of 1. 3 ～ 3. 5 times of the existing implementation and reduces hardware consumption. It can be effectively used in practical high-throughput communication systems.
引文
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[13]Peng Hao,Liu Rongke,Hou Yi,et al. A Gb/s parallel block-based Viterbi decoder for convolutional codes on GPU[C]//Proc of the 8th International Conference on Wireless Communications&Signal Processing. Piscataway,NJ:IEEE Press,2016:1-6.
[14]Xia Kaifeng,WU Bin,Xiong Tao,et al. Design of a high-throughput sliding block Viterbi decoder for IEEE 802. 11ac WLAN systems[J]. IEICE Trans on Fundamentals of Electronics Communications&Computer Sciences,2017,E100. A(8):1606-1614.
[2] Li Lifu,Li Haiwen,Li Hongliang,et al. Research and implementation of Viterbi decoding in TD-LTE system[C]//Advanced Information Technology,Electronic and Automation Control Conference. Piscataway,NJ:IEEE Press,2017:890-894.
[3]罗友宝,李小文. LTE系统的Viterbi译码算法仿真及DSP实现[J].光通信研究,2010(3):67-70.(Luo Youbao,Li Xiaowen.Simulation and DSP realization of Viterbi decoding algorithm in LTE systems[J]. Study on Optical Communications,2010(3):67-70.)
[4] Stamoulias I,Georgoulakis K,Blionas S,et al. FPGA implementation of an MLSE equalizer in 10 Gbps optical links[C]//Proc of IEEE International Conference on Digital Signal Processing. Piscataway,NJ:IEEE Press,2015:794-798.
[5] Wu M,Sun Yang,Wang Guohui,et al. Implementation of a high throughput 3GPP turbo decoder on GPU[J]. Journal of Signal Processing Systems,2011,65(2):171-183.
[6] Martínez-Zaldívar F J. Tridimensional block multiword LDPC decoding on GPUs[J]. Journal of Supercomputing,2011,58(3):314-322.
[7] Wu M,Sun Yang,Gupta S,et al. Implementation of a high throughput soft MIMO detector on GPU[J]. Journal of Signal Processing Systems,2011,64(1):123-136.
[8] Liu Chengjun,Bie Zhisong,Chen Canfeng,et al. A parallel LTE turbo decoder on GPU[C]//Proc of the 15 th IEEE International Conference on Communication Technology. Piscataway,NJ:IEEE Press,2014:609-614.
[9] Lin C S,Liu W L,Yeh W T,et al. A tiling-scheme Viterbi decoder in software defined radio for GPUs[C]//Proc of the 7th International Conference on Wireless Communications, Networking and Mobile Computing. Piscataway,NJ:IEEE Press,2011:1-4.
[10] Zhang Dan,Zhao Rongcai,Han Lin,et al. An implementation of Viterbi algorithm on GPU[C]//Proc of the 1st International Conference on Information Science and Engineering. Piscataway,NJ:IEEE Press,2009:121-124.
[11]Ahn C,Kim J,Ju J,et al. Implementation of an SDR platform using GPU and its application to a 2×2 MIMO Wi MAX system[J]. Analog Integrated Circuits&Signal Processing,2011,69(2-3):107-117.
[12]Li Rongchun,Dou Yong,Zou Dan. Efficient parallel implementation of three-point Viterbi decoding algorithm on CPU,GPU,and FPGA[J]. Concurrency&Computation Practice&Experience,2014,26(3):821-840.
[13]Peng Hao,Liu Rongke,Hou Yi,et al. A Gb/s parallel block-based Viterbi decoder for convolutional codes on GPU[C]//Proc of the 8th International Conference on Wireless Communications&Signal Processing. Piscataway,NJ:IEEE Press,2016:1-6.
[14]Xia Kaifeng,WU Bin,Xiong Tao,et al. Design of a high-throughput sliding block Viterbi decoder for IEEE 802. 11ac WLAN systems[J]. IEICE Trans on Fundamentals of Electronics Communications&Computer Sciences,2017,E100. A(8):1606-1614.