摘要
基于0.18μm CMOS工艺,设计并实现了一种5位高精度低附加相移数控衰减器。该衰减器的衰减动态范围为15.5 dB,步进为0.5 dB。采用了T型衰减结构和SPDT型衰减结构的衰减网络。采用了悬浮栅和悬浮衬底,提高了衰减精度,减小了插入损耗。采用了相位补偿网络,有效降低了衰减器的附加相移。测试结果表明,在24~30 GHz频带范围内,衰减步进为0.5 dB,插入损耗小于8 dB,衰减误差均方根(RMS)小于0.45 dB,附加相移小于±5°。芯片尺寸为1.2 mm×0.3 mm。
A 5-bit high accuracy low phase error digital attenuator was designed and implemented in a 0.18 μm CMOS technology. The digital attenuator had a dynamic attenuation range of 15.5 dB with a step resolution of 0.5 dB. Attenuation structures of T-type and SPDT-type were chosen for the attenuation networks. The floating gate and floating body was applied to enhance the attenuation accuracy and reduce the insertion loss. A phase compensation network was applied to reduce the phase error. In the 24~30 GHz pass band, the results showed that the attenuation step was 0.5 dB, the insertion loss was less than 8 dB, the attenuation amplitude error(RMS) was 0.45 dB, and the phase error was ±5°. The total chip size was 1.2 mm×0.3 mm.
引文
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