众核处理器访存链路接口的FPGA验证
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摘要
面向众核处理器提出一种访存链路接口的现场可编程门阵列(Field-Programmable Gate Array,FPGA)验证平台,用于对处理器访存链路关键部件进行功能及可靠性测试。提出片上读写激励自动产生与检查机制、以太网接口硬件用户数据报协议(User Datagram Protocol,UDP)协议栈和FPGA芯片间多通道并行链路三项关键技术并进行设计实现。实验结果表明提出的各项关键技术功能正确,不仅丰富了功能验证中随机激励产生及结果验证的手段,而且实现了对链路数据检错和多lane间延迟偏斜纠正逻辑的可靠性测试与评估。经过该平台验证的访存链路接口在实际芯片中通过了功能正确性测试,证明了验证的有效性。
An FPGA( field-programmable gate array) verification platform for memory link interface of many-core processor was proposed to test the function and reliability of the main components of the processor' s memory access link. Three key technologies,the on-chip read-write requests automatic generation and result checking mechanism,the hardware UDP( user datagram protocol) protocol stack in Ethernet interface and the multi-lane parallel link between FPGA chips were proposed and implemented. Experiments on the platform show that the proposed technologies are correct,they not only enrich the ways of the random request generation and result checking for functional verification,but also can test and evaluate the logics of link errors detection and lane-to-lane deskew. The proposed platform has been used to verify a real many-core processor in which the function of memory link interface is correct,so the validity of the verification is proved.
An FPGA( field-programmable gate array) verification platform for memory link interface of many-core processor was proposed to test the function and reliability of the main components of the processor' s memory access link. Three key technologies,the on-chip read-write requests automatic generation and result checking mechanism,the hardware UDP( user datagram protocol) protocol stack in Ethernet interface and the multi-lane parallel link between FPGA chips were proposed and implemented. Experiments on the platform show that the proposed technologies are correct,they not only enrich the ways of the random request generation and result checking for functional verification,but also can test and evaluate the logics of link errors detection and lane-to-lane deskew. The proposed platform has been used to verify a real many-core processor in which the function of memory link interface is correct,so the validity of the verification is proved.
引文
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[2]周宏伟,邓让钰,李永进,等.多核处理器验证中存储数据错误快速定位方法[J].国防科技大学学报,2012,34(6):1-6.ZHOU Hongwei,DENG Rangyu,LI Yongjin,et al.A fast location mechanism on memory data error for multi-core processors verification[J].Journal of National University of Defense Technology,2012,34(6):1-6.(in Chinese)
[3]S2C Inc.Prodigy complete prototyping platform[EB/OL].(2016-12-10)[2016-12-20].http://www.s2cinc.com/products/prodigy-complete-prototyping-platform.
[4]郭阳,李暾,李思昆.微处理器功能验证方法研究[J].计算机工程与应用,2003,39(5):35-37.GUO Yang,LI Tun,LI Sikun.Functional verification methodology for microprocessor[J].Computer Engineering and Applications,2003,39(5):35-37.(in Chinese)
[5]张珩.通用处理器设计中硬件仿真验证[J].计算机工程与应用,2007,43(8):1-3,233.ZHANG Heng.Hardware simulation for microprocessor verification[J].Computer Engineering and Applications,2007,43(8):1-3,233.(in Chinese)
[6]黄晓林,潘红兵,易伟,等.基于多FPGA的No C多核处理器验证平台设计[J].计算机工程与设计,2012,33(1):180-185.HUANG Xiaolin,PAN Hongbing,YI Wei,et al.Design of multi-FPGA-based multi-core processor No C verification platform[J].Computer Engineering and Design,2012,33(1):180-185.(in Chinese)
[7]郭阳,李思昆,屈婉霞.片上多核处理器验证:挑战、现状与展望[J].计算机辅助设计与图形学学报,2012,24(12):1521-1532.GUO Yang,LI Sikun,QU Wanxia.Verification of on-chip multi-core processor:challenges,status,forecasts[J].Journal of Computer-Aided Design&Computer Graphics,2012,24(12):1521-1532.(in Chinese)
[8]Starke W J,Stuecheli J,Daly D M,et al.The cache and memory subsystems of the IBM POWER8 processor[J].IBM Journal of Research&Development,2015,59(1):1-13.
[9]Pawlowski J T.Hybrid memory cube(HMC)[C]//Proceedings of the 23th Hot Chips Conference,2011:1-24.