一种任意比率电子齿轮分频器的实现方法
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摘要
针对滚齿机数控系统电子齿轮箱的设计要求,提出了一种根据现场可编程门阵列和Bresenham算法的任意比率电子齿轮分频器的实现方法。该方法的实现原理是将计算机图形学上描绘由两点所决定的直线的算法应用到电子齿轮的脉冲频率分频上,采用硬件描述语言来实现电子齿轮分频。该方法对Bresenham算法进行了改进,将累计误差值和溢出斜率修改为整数,使算法只涉及整数的加减运算,因此更快捷、更可靠。软件仿真和实验结果表明,所提出的电子齿轮分频方法可使分频过程更为简便,不仅减少了硬件资源耗费,而且算法具有较强的实用性。
A new electronic gear based on Bresenham algorithm and field-programmable gate array(FPGA)is presented to realize the arbitrary ratio fractional frequency for the design of hobbing machine CNC system.The basic principle of this realization method determines the order to form a closer approximation to a straight line between two given points,which is usually used to draw lines on a computer screen,and applied for fractional frequency divider at arbitrary ratio in hardwere description language(HDL)on the FPGA.This new algorithm eliminates expensive multiplications and divisions as well as numerical scaling to integer-only arithmetic,so achieves high efficiency and good stability.Generic synthesizable Verilog-HDL design following this algorithm is simulated on Quartus II system and examined by synthesis examples on CNC system.
A new electronic gear based on Bresenham algorithm and field-programmable gate array(FPGA)is presented to realize the arbitrary ratio fractional frequency for the design of hobbing machine CNC system.The basic principle of this realization method determines the order to form a closer approximation to a straight line between two given points,which is usually used to draw lines on a computer screen,and applied for fractional frequency divider at arbitrary ratio in hardwere description language(HDL)on the FPGA.This new algorithm eliminates expensive multiplications and divisions as well as numerical scaling to integer-only arithmetic,so achieves high efficiency and good stability.Generic synthesizable Verilog-HDL design following this algorithm is simulated on Quartus II system and examined by synthesis examples on CNC system.
引文
[1]胡赤兵,田芳勇,姜衍仓.电子齿轮箱在非圆齿轮滚齿加工中的应用[J].机械设计与制造,2009(12):79-81.HU Chibing,TIAN Fangyong,JIANG Yancang.Application of the electrical gearbox in the hobbing noncircular gear[J].Machinery Design&Manufacture,2009(12):79-81.
[2]DINSDALE J,JONES P F,Thorneycroft M.The electronic gearbox-computer software replaces mechanical couplings[J].CIRP Annals:Manufacturing Technology,1982,31(1):247-249.
[3]TIAN Hongli,SHI Shuo.Controllable arbitrary integer frequency divider based on VHDL[C]∥2009International Joint Conference on Artificial Intelligence.Amsterdam,Netherlands:Artificial Intelligence,2009:691-694.
[4]SEONCHEOL K,YOUNGSIK K.A fractional-NPLL frequency synthesizer design[C]∥Proceedings of the IEEE Southeast Conference 2005.Piscataway,NJ,USA:IEEE,2005:84-87.
[5]滕福林,李宏胜,温秀兰,等.电子齿轮比对轮廓误差及加工效率影响的研究[J].中国机械工程,2012,23(13):1607-1610.TENG Fulin,LI Hongsheng,WEN Xiulan,et al.Research on influences on contour error and cutting efficiency from electrical gear-ratio[J].Chinese Mechanical Engineering,2012,23(13):1607-1610.
[6]常兴旺,李孝辉,王玉兰,等.基于FPGA的小数分频的研究与设计[J].电子测量与仪器学报,2009(增刊):253-255.CHANG Xingwang,LI Xiaohui,WANG Yulan,et al.Design of decimal fraction frequency divider based on FPGA technology[J].Journal of Electronic Measurement and Instrument,2009(Supplement):253-255.
[7]冯焱,周海东,忤婷,等.多模式定位系统接收机中的分数频率综合器[J].西安交通大学学报,2011,43(12):35-39.FENG Yan,ZHOU Haidong,WU Ting,et al.A fractional-n frequency synthesizer for multi-mode positioning system receivers[J].Journal of Xi’an Jiaotong University,2011,43(12):35-39.
[8]GU Liangling,ZHOU Nanquan.Research of frequency divider based on programmable logic device[J].Procedia Environmental Sciences,2011,10:820-824.
[9]HU Xiaoping,LIN Yunfeng.Realization on decimal frequency divider based on FPGA and Quartus II[C]∥Communication in Computer and Information Science.Berlin,German:Springer,2011:350-356.
[10]尹辉炳,张涛.基于VHDL的全数字分数分频器设计[J].科学技术与工程,2006,6(12):1609-1611.YIN Huibing,ZHANG Tao.The design of total digitized fractional frequency divider based on VHDL[J].Science Technology and Engineering,2006,6(12):1609-1611.
[11]PREUBER T B,SPALLEK R G.Analysis of a fullyscalable digital fractional clock divider[C]∥International Conference on Application-specific Systems.Samos,Greece:Architectures and Processors,2006:133-177.
[12]JACK E B.Algorithm for computer control of a digital plotter[J].IBM Systems Journal,1965,4(1):25-30.
[2]DINSDALE J,JONES P F,Thorneycroft M.The electronic gearbox-computer software replaces mechanical couplings[J].CIRP Annals:Manufacturing Technology,1982,31(1):247-249.
[3]TIAN Hongli,SHI Shuo.Controllable arbitrary integer frequency divider based on VHDL[C]∥2009International Joint Conference on Artificial Intelligence.Amsterdam,Netherlands:Artificial Intelligence,2009:691-694.
[4]SEONCHEOL K,YOUNGSIK K.A fractional-NPLL frequency synthesizer design[C]∥Proceedings of the IEEE Southeast Conference 2005.Piscataway,NJ,USA:IEEE,2005:84-87.
[5]滕福林,李宏胜,温秀兰,等.电子齿轮比对轮廓误差及加工效率影响的研究[J].中国机械工程,2012,23(13):1607-1610.TENG Fulin,LI Hongsheng,WEN Xiulan,et al.Research on influences on contour error and cutting efficiency from electrical gear-ratio[J].Chinese Mechanical Engineering,2012,23(13):1607-1610.
[6]常兴旺,李孝辉,王玉兰,等.基于FPGA的小数分频的研究与设计[J].电子测量与仪器学报,2009(增刊):253-255.CHANG Xingwang,LI Xiaohui,WANG Yulan,et al.Design of decimal fraction frequency divider based on FPGA technology[J].Journal of Electronic Measurement and Instrument,2009(Supplement):253-255.
[7]冯焱,周海东,忤婷,等.多模式定位系统接收机中的分数频率综合器[J].西安交通大学学报,2011,43(12):35-39.FENG Yan,ZHOU Haidong,WU Ting,et al.A fractional-n frequency synthesizer for multi-mode positioning system receivers[J].Journal of Xi’an Jiaotong University,2011,43(12):35-39.
[8]GU Liangling,ZHOU Nanquan.Research of frequency divider based on programmable logic device[J].Procedia Environmental Sciences,2011,10:820-824.
[9]HU Xiaoping,LIN Yunfeng.Realization on decimal frequency divider based on FPGA and Quartus II[C]∥Communication in Computer and Information Science.Berlin,German:Springer,2011:350-356.
[10]尹辉炳,张涛.基于VHDL的全数字分数分频器设计[J].科学技术与工程,2006,6(12):1609-1611.YIN Huibing,ZHANG Tao.The design of total digitized fractional frequency divider based on VHDL[J].Science Technology and Engineering,2006,6(12):1609-1611.
[11]PREUBER T B,SPALLEK R G.Analysis of a fullyscalable digital fractional clock divider[C]∥International Conference on Application-specific Systems.Samos,Greece:Architectures and Processors,2006:133-177.
[12]JACK E B.Algorithm for computer control of a digital plotter[J].IBM Systems Journal,1965,4(1):25-30.