应用于低压锁相环的高性能可编程电荷泵
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摘要
提出了一种应用于低压锁相环的输出电流可编程电荷泵.该电荷泵由两个子电荷泵电路组成.每个子电荷泵都采用了反馈控制和复制偏置技术来保证输出的充/放电电流有接近理想的匹配性.利用电流求和结构,两子电荷泵在宽输出电压范围内输出电流的变化被相互补偿,从而得到相对恒定的总电流.该电荷泵可以编程输出从50μA到1.55mA变化的电流,并以50μA为最小步进.在0.1V到1.05V的宽输出电压范围内,基于0.13μm CMOS工艺的后仿真结果显示输出电流的失配率和变化率被分别限制在0.15%和5%以内.精确的匹配特性极大地减小了锁相环的静态相位误差和参考杂散,同时恒定的输出电流有利于稳定锁相环的动态特性,所以该电荷泵能满足低压宽带锁相环的应用要求.
This paper proposes a charge pump with a programmable output current for low voltage phaselocked loops(PLLs).It consists of two sub-units both of which leverage replica bias and feedback control techniques to achieve perfect match between charging and discharging currents.With the help of the current summing structure,the output current variation in each sub charge pump can be compensated by the other.Thus,their sum current remains relatively constant in a wide output voltage range.The charge pump can be programmed to output a 50μA~1.55 mA current,with a 50μA minimum step.It is designed in a 0.13μm CMOS process and the post-layout simulation demonstrates the total current mismatch and variation rates are limited in 0.15%and 5%,over the output voltage range of 0.1~1.05 V.Such precise matching greatly suppresses the reference spur and static phase error,and the good current constancy is favorable for dynamic design.Both features render our design suitable for low voltage PLLs.
This paper proposes a charge pump with a programmable output current for low voltage phaselocked loops(PLLs).It consists of two sub-units both of which leverage replica bias and feedback control techniques to achieve perfect match between charging and discharging currents.With the help of the current summing structure,the output current variation in each sub charge pump can be compensated by the other.Thus,their sum current remains relatively constant in a wide output voltage range.The charge pump can be programmed to output a 50μA~1.55 mA current,with a 50μA minimum step.It is designed in a 0.13μm CMOS process and the post-layout simulation demonstrates the total current mismatch and variation rates are limited in 0.15%and 5%,over the output voltage range of 0.1~1.05 V.Such precise matching greatly suppresses the reference spur and static phase error,and the good current constancy is favorable for dynamic design.Both features render our design suitable for low voltage PLLs.
引文
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[10]HATI M K,BHATTACHARY T K.A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 0.13-μm CMOS[C]//International Conference on VLSI Systems,Architecture,Technology and Applications.Piscataway:IEEE,2015:1-6.
[11]TSITUORAS A,PLESSAS F,BIRBAS M,et al.A 1V CMOS Programmable Accurate Charge Pump With Wide Output Voltage Range[J].Microelectronics Journal,2011,42(9):1082-1089.
[2]GAIED D,HEGAZI E.Charge-pump Folded Noise Cancelation in Fractional-N Phase-Locked Loop[J].IEEE Transactions on Circuits and System II:Express Briefs,2014,61(6):378-382.
[3]MOON J W,CHOI K CI,CHOI W Y.A 0.4V,90~350-MHz PLL with an Active Loop-filter Charge Pump[J].IEEE Transactions on Circuits and System II:Express Briefs,2014,61(5):319-323.
[4]YOSHIMURA T,IWADE S,MAKINO H,et al.Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-locked Loop[J].IEEE Transactions on Circuits and System I:Regular Papers,2013,60(4):896-907.
[5]冯焱,罗阳,陈贵灿.具有稳定环路带宽功能的多模分数频率综合器[J].西安电子科技大学学报,2013,40(5):119-123.FENG Yan,LUO Yang,CHEN Guican.Multi-mode Fractional-N Frequency Synthesizer with a stabilized loop bandwidth[J].Journal of Xidian University,2013,40(5):119-123.
[6]KAMAL N,AL-SARAWI S F,ABBOTT D.Reference Spur Suppression Technique using Ratioed Current Charge Pump[J].Electronics Letters,2013,49(12):746-747.
[7]ZHOU J Z,WANG Z G.A High-performance CMOS Charge-pump for Phase-locked Loops[C]//Proceedings of the International Conference on Microwave and Millimeter Wave Technology:2.Piscataway:IEEE,2008:839-842.
[8]JORAM N,WOLF R,ELLINGER F.High Swing PLL Charge Pump with Current Mismatch Reduction[J].Electronics Letters,2014,50(9):661-663.
[9]YAN H,QIN P,CHEN D P.A New Phase Noise Cancelling Technique for Fractional-N PLL[C]//IEEE International Conference on Solid-State and Integrated Circuit Technology.Piscataway:IEEE,2014:1-3.
[10]HATI M K,BHATTACHARY T K.A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 0.13-μm CMOS[C]//International Conference on VLSI Systems,Architecture,Technology and Applications.Piscataway:IEEE,2015:1-6.
[11]TSITUORAS A,PLESSAS F,BIRBAS M,et al.A 1V CMOS Programmable Accurate Charge Pump With Wide Output Voltage Range[J].Microelectronics Journal,2011,42(9):1082-1089.