高速逐次逼近型模数转换器的研究与设计
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摘要
本文采用HLMC 55nm工艺,设计了一款高速逐次逼近型模数转换器。为了提高模数转换器的转换速度,在设计中采用了特殊的电容阵列布局方式,减小高位电容降低电容DAC对建立时间和建立精度的要求;采用快复位式比较器减小比较器的比较延迟;采用编程可控的环路延迟,控制环路建立的精度和速度。在80MHz输入采样时钟的频率下,测试得到的有效位数超过8.2bit。
A high-speed Successive Approximation Register Analog to Digital Converter is designed with HLMC55 nm technology. To meet settling and resolution requirements, special arrangement of capacitor array, small capacitor unit and fast-reset comparator are adopted in this work. Meanwhile a programmable delay control block is inserted in feedback loop to improve the settling of MSB. With 80 MHz sampling rate, the measured enob is 8.2 bits.
A high-speed Successive Approximation Register Analog to Digital Converter is designed with HLMC55 nm technology. To meet settling and resolution requirements, special arrangement of capacitor array, small capacitor unit and fast-reset comparator are adopted in this work. Meanwhile a programmable delay control block is inserted in feedback loop to improve the settling of MSB. With 80 MHz sampling rate, the measured enob is 8.2 bits.
引文
[1]Liu,C.C.,S.J.Chang,G.Y.Huang,and Y.Z.Lin.A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J].IEEE Journal of Solid-State circuits,2010,45(4),731-740.
[2]F.Kuttner,“A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,”ISSCC Dig.Tech.Papers,pp.176-177,Feb.,2002.
[3]J.Craninckx and G.Van der Plas,“A 65f J/Conversion-Step 0-to-50MS/s 0-to-0.7m W 9b Charge-sharing SAR ADC in 90nm Digital CMOS,”ISSCC Dig.Tech.Papers,pp.246-247,Feb,2007.
[4]Louwsma,S.,A.van Tuijl,M.Vertregt,and B.Nauta.A 1.35 GS/s,10 b,175 m W time-interleaved ad converter in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2008,43,778-786.
[5]F.Kuttner,“A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,”ISSCC Dig.Tech.Papers,pp.176-177,Feb.,2002.
[6]Tsai J H,Wang H H,Yen Y C,et al.A 0.003 mm210b 240 MS/s 0.7 m W SAR ADC in 28 nm CMOS With Digital Error Correction and correlated-Reversed Switching[J].IEEE Journal of Solid-State Circuits,2015,50(6):1382-1398.
[7]W.Liu,P.Huang,and Y.Chiu,“A 12 b 22.5/45MS/s 3.0Mw 0.059 mm2CMOS SAR ADC achieving over 90d B SFDR,”IEEE ISSCC Dig.Tech.Papers,Feb.2010,380-381.
[8]R.Kapusta,J.Shen,S.Decker,H.Li,and E.Ibaragi,“A 14b 80MS/s SAR ADC with 73.6d B SNDR in65nm CMOS,”IEEE ISSCC Dig.Tech.Papers,Feb.2013,472-473.
[2]F.Kuttner,“A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,”ISSCC Dig.Tech.Papers,pp.176-177,Feb.,2002.
[3]J.Craninckx and G.Van der Plas,“A 65f J/Conversion-Step 0-to-50MS/s 0-to-0.7m W 9b Charge-sharing SAR ADC in 90nm Digital CMOS,”ISSCC Dig.Tech.Papers,pp.246-247,Feb,2007.
[4]Louwsma,S.,A.van Tuijl,M.Vertregt,and B.Nauta.A 1.35 GS/s,10 b,175 m W time-interleaved ad converter in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2008,43,778-786.
[5]F.Kuttner,“A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,”ISSCC Dig.Tech.Papers,pp.176-177,Feb.,2002.
[6]Tsai J H,Wang H H,Yen Y C,et al.A 0.003 mm210b 240 MS/s 0.7 m W SAR ADC in 28 nm CMOS With Digital Error Correction and correlated-Reversed Switching[J].IEEE Journal of Solid-State Circuits,2015,50(6):1382-1398.
[7]W.Liu,P.Huang,and Y.Chiu,“A 12 b 22.5/45MS/s 3.0Mw 0.059 mm2CMOS SAR ADC achieving over 90d B SFDR,”IEEE ISSCC Dig.Tech.Papers,Feb.2010,380-381.
[8]R.Kapusta,J.Shen,S.Decker,H.Li,and E.Ibaragi,“A 14b 80MS/s SAR ADC with 73.6d B SNDR in65nm CMOS,”IEEE ISSCC Dig.Tech.Papers,Feb.2013,472-473.