基于异步时钟的SoC功耗约束测试调度优化
|
摘要
测试调度是一种能有效减少片上系统(system-on-chip,SoC)测试耗时(test application time,TAT)以降低测试成本的经典技术.然而,随着功耗问题的日益加剧,功耗约束成为测试调度中必须考虑的重要问题.可以调节各测试周期长度的异步时钟测试在对单个电路进行测试用时优化时效果显著,但直接将其应用于SoC测试调度并非总能获得最优的调度结果,使用传统测试调度模型往往会产生明显非最优的结果.在结合图论中团(clique)的概念,并分析异步时钟机制的特点后,提出一种将异步时钟特性应用于功耗约束SoC测试调度的方案.使用测试兼容图(test compatibility graph,TCG)和混合整型线性规划(mixed integer linear programming,MILP)建立相对应数学模型,理论分析和在ITC02基准SoC集上的模拟实验结果表明,该方案能有效地减少测试耗时.
Test cost of very large scale integration(VLSI)circuits is highly related to the test application time(TAT).Test scheduling is an effective technique to reduce the TAT of testing a SoC,which has been studied for decades.However,increasing power issues and consequences have made power-aware test necessary and important.Power-constrained test scheduling is one of the promising methods.Recently asynchronous clock test which can vary the clock period of each test cycle has been developed and shown great potential in TAT reduction for single circuit.However,applying such features to SoC test scheduling is not straight forward.Using conventional test scheduling model may lead to inferior results and longer scheduling time.After analyzing the characteristics of asynchronous clock test and power-constrained test scheduling problems,we propose a method to exploit asynchronous clock to SoC test scheduling based on clique.The resource constraint among each tests is represented by test-compatibility-graph(TCG);the scheduling problem is formed using mixed-integer linear programming(MILP)model;and the problem is solved by stateof-the-art mathematical programming solver.The results of both theoretical analysis and simulation experiment on the ITC'02 benchmarks show that combining test scheduling technique with asynchronous clock can reduce TAT effectively and the proposed method can optimize the scheduling problem even further.
Test cost of very large scale integration(VLSI)circuits is highly related to the test application time(TAT).Test scheduling is an effective technique to reduce the TAT of testing a SoC,which has been studied for decades.However,increasing power issues and consequences have made power-aware test necessary and important.Power-constrained test scheduling is one of the promising methods.Recently asynchronous clock test which can vary the clock period of each test cycle has been developed and shown great potential in TAT reduction for single circuit.However,applying such features to SoC test scheduling is not straight forward.Using conventional test scheduling model may lead to inferior results and longer scheduling time.After analyzing the characteristics of asynchronous clock test and power-constrained test scheduling problems,we propose a method to exploit asynchronous clock to SoC test scheduling based on clique.The resource constraint among each tests is represented by test-compatibility-graph(TCG);the scheduling problem is formed using mixed-integer linear programming(MILP)model;and the problem is solved by stateof-the-art mathematical programming solver.The results of both theoretical analysis and simulation experiment on the ITC'02 benchmarks show that combining test scheduling technique with asynchronous clock can reduce TAT effectively and the proposed method can optimize the scheduling problem even further.
引文
[1]Hu Yu,Han Yinhe,Li Xiaowei.Design-for-testability and test technologies for system-on-a-chip[J].Journal of Computer Research and Development,2005,42(1):153-162(in Chinese)(胡瑜,韩银和,李晓维.SoC可测试性设计与测试技术[J].计算机研究与发展,2005,42(1):153-162)
[2]Kime C R,Saluja K K.Test scheduling in testable VLSI circuits[C]//Proc of the 25th Int Symp on Fault Tolerant Computing.Piscataway,NJ:IEEE,1995:406-412
[3]Chou R M,Saluja K K,Agrawal D D.Scheduling tests for VLSI systems under power constraints[J].IEEE Trans on Very Large Scale Integration Systems,1997,5(2):175-185
[4]Iyengar V,Chakrabarty K,Marinissen E J.On using rectangle packing for SOC wrapper/TAM co-optimization[C]//Proc of the 20th VLSI Test Symp.Piscataway,NJ:IEEE,2002:253-258
[5]Chakrabarty K.Test scheduling for core-based systems using mixed integer linear programming[J].IEEE Trans on Computers-Aided Design of Integrated Circuits and Systems,2002,19(10):1163-1174
[6]Hu Yu,Han Yinhe,Li Huawei,et al.SoC test scheduling based on scan chain balance of pair cores[J].Journal of Computer-Aided Design &Computer Graphics,2005,17(10):2203-2208(in Chinese)(胡瑜,韩银和,李华伟,等.基于双核扫描链平衡的SoC测试调度[J].计算机辅助设计与图形学学报,2005,17(10):2203-2208)
[7]Zou W,Reddy S M,Pomeranz I,et al.SoC test scheduling using simulated annealing[C]//Proc of the 21st VLSI Test Symp.Piscataway,NJ:IEEE,2003:325-330
[8]Giri C,Kumar D,Tipparthi R,et al.A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraint[J].WSEAS Trans on Circuits and Systems,2008,7(5):416-427
[9]Millican S K,Saluja K K.Formulating optimal test scheduling problem with dynamic voltage and frequency scaling[C]//Proc of the 22nd Asian Test Symp.Piscataway,NJ:IEEE,2013:165-170
[10]Kavousianos X,Chakrabarty K,Jain A,et al.Test scheduling for multicore SoCs with dynamic voltage scaling and multiple voltage islands[C]//Proc of the 20th Asian Test Symp.Piscataway,NJ:IEEE,2011:33-39
[11]Ling L,Jiang J.Exploit dynamic voltage and frequency scaling for SoC test scheduling under thermal constraints[C]//Proc of the 23rd Asian Test Symp.Piscataway,NJ:IEEE,2014:180-185
[12]Venkataramani P,Agrawal V D.ATE test time reduction using asynchronous clock period[C]//Proc of the 2013IEEE Int Test Conf.Piscataway,NJ:IEEE,2013:1-10
[13]Marinissen E,Iyengar E,Chakrabarty K.A set of benchmarks for modular testing of SoCs[C]//Proc of the2002IEEE Int Test Conf.Piscataway,NJ:IEEE,2002:521-528
[14]Bild D,Misra S,Chantem T,et al.Temperature-aware test scheduling for multiprocessor system-on-chip[C]//Proc of the 2008 IEEE Int Conf on Computer-Aided Design.Piscataway,NJ:IEEE,2008:59-66
[15]Sheshardi V,Agrawal V D,Agrawal P.Optimal powerconstrained SoC test schedules with customizable clock rates[C]//Proc of the 2012IEEE Int Symp on SoC.Piscataway,NJ:IEEE,2012:271-276
[16]Sheshardi V,Agrawal V,Agrawal P.Optimum test schedule for SoC with specified clock frequencies and supply voltages[C]//Proc of the 12th Int Conf on VLSI Design.Piscataway,NJ:IEEE,2013:267-272
[17]Shanmugasundaram P,Agrawal V D.Dynamic scan clock control for test time reduction maintaining peak power limit[C]//Proc of the 30th VLSI Test Symp.Piscataway,NJ:IEEE,2012:248-253
[18]Millican S K,Saluja K K.3D-IC benchmarks[OL].2013[2014-06-27].http://3dsocbench.ece.wisc.edu
[19]Lfberg J.YALMIP:A toolbox for modeling and optimization in MATLAB[C/OL]//Proc of the 2004IEEE CACSD Conf.2004[2014-06-27].http://users.isy.liu.se/johanl/yalmip
[20]Optimization G.Gurobi optimizer reference manual[OL].2012[2014-06-27].http://www.gurobi.com
[2]Kime C R,Saluja K K.Test scheduling in testable VLSI circuits[C]//Proc of the 25th Int Symp on Fault Tolerant Computing.Piscataway,NJ:IEEE,1995:406-412
[3]Chou R M,Saluja K K,Agrawal D D.Scheduling tests for VLSI systems under power constraints[J].IEEE Trans on Very Large Scale Integration Systems,1997,5(2):175-185
[4]Iyengar V,Chakrabarty K,Marinissen E J.On using rectangle packing for SOC wrapper/TAM co-optimization[C]//Proc of the 20th VLSI Test Symp.Piscataway,NJ:IEEE,2002:253-258
[5]Chakrabarty K.Test scheduling for core-based systems using mixed integer linear programming[J].IEEE Trans on Computers-Aided Design of Integrated Circuits and Systems,2002,19(10):1163-1174
[6]Hu Yu,Han Yinhe,Li Huawei,et al.SoC test scheduling based on scan chain balance of pair cores[J].Journal of Computer-Aided Design &Computer Graphics,2005,17(10):2203-2208(in Chinese)(胡瑜,韩银和,李华伟,等.基于双核扫描链平衡的SoC测试调度[J].计算机辅助设计与图形学学报,2005,17(10):2203-2208)
[7]Zou W,Reddy S M,Pomeranz I,et al.SoC test scheduling using simulated annealing[C]//Proc of the 21st VLSI Test Symp.Piscataway,NJ:IEEE,2003:325-330
[8]Giri C,Kumar D,Tipparthi R,et al.A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraint[J].WSEAS Trans on Circuits and Systems,2008,7(5):416-427
[9]Millican S K,Saluja K K.Formulating optimal test scheduling problem with dynamic voltage and frequency scaling[C]//Proc of the 22nd Asian Test Symp.Piscataway,NJ:IEEE,2013:165-170
[10]Kavousianos X,Chakrabarty K,Jain A,et al.Test scheduling for multicore SoCs with dynamic voltage scaling and multiple voltage islands[C]//Proc of the 20th Asian Test Symp.Piscataway,NJ:IEEE,2011:33-39
[11]Ling L,Jiang J.Exploit dynamic voltage and frequency scaling for SoC test scheduling under thermal constraints[C]//Proc of the 23rd Asian Test Symp.Piscataway,NJ:IEEE,2014:180-185
[12]Venkataramani P,Agrawal V D.ATE test time reduction using asynchronous clock period[C]//Proc of the 2013IEEE Int Test Conf.Piscataway,NJ:IEEE,2013:1-10
[13]Marinissen E,Iyengar E,Chakrabarty K.A set of benchmarks for modular testing of SoCs[C]//Proc of the2002IEEE Int Test Conf.Piscataway,NJ:IEEE,2002:521-528
[14]Bild D,Misra S,Chantem T,et al.Temperature-aware test scheduling for multiprocessor system-on-chip[C]//Proc of the 2008 IEEE Int Conf on Computer-Aided Design.Piscataway,NJ:IEEE,2008:59-66
[15]Sheshardi V,Agrawal V D,Agrawal P.Optimal powerconstrained SoC test schedules with customizable clock rates[C]//Proc of the 2012IEEE Int Symp on SoC.Piscataway,NJ:IEEE,2012:271-276
[16]Sheshardi V,Agrawal V,Agrawal P.Optimum test schedule for SoC with specified clock frequencies and supply voltages[C]//Proc of the 12th Int Conf on VLSI Design.Piscataway,NJ:IEEE,2013:267-272
[17]Shanmugasundaram P,Agrawal V D.Dynamic scan clock control for test time reduction maintaining peak power limit[C]//Proc of the 30th VLSI Test Symp.Piscataway,NJ:IEEE,2012:248-253
[18]Millican S K,Saluja K K.3D-IC benchmarks[OL].2013[2014-06-27].http://3dsocbench.ece.wisc.edu
[19]Lfberg J.YALMIP:A toolbox for modeling and optimization in MATLAB[C/OL]//Proc of the 2004IEEE CACSD Conf.2004[2014-06-27].http://users.isy.liu.se/johanl/yalmip
[20]Optimization G.Gurobi optimizer reference manual[OL].2012[2014-06-27].http://www.gurobi.com