阵列探测器L1触发系统加法电路优化设计
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摘要
针对兰州重离子加速器外靶终端硅微条阵列探测器L1触发系统,设计了一个基于Xilinx7系列FPGA芯片的改进加法逻辑电路,利用快速进位链结构,对加法电路模块进行优化。对优化后加法电路结构和同类传统加法电路比较,并对逻辑时延进行和结构性能建模分析。仿真和测试结果表明:优化后模块逻辑时延3 ns左右,相比传统加法逻辑,系统死时间低,有效采集事例率高,能够满足L1触发系统的要求。
Focused on the level 1 sub- trigger system in Silicon micro- strip array detector of the Cooling Storage Ring on the Heavy Ion Research Facility in Lanzhou( HIRFL- CSR),in this paper,based on the structural features of Xilinx 7 series FPGA chip,an improved design of logic circuit for the adder module is proposed,fast carry logic adder is employed and a new trigger judgment circuit is developed. Compared with the traditional adder circuit and the optimized,modeling analyses of structural performance and logic dead- time,the circuit was simulated and tested. The dead time of improved module is reduced to about 3 ns. Compared with other types of adder circuit structures,the signal processing time of new trigger judgment circuit is reduced,and the effective acquisition rate is increased,thus,the total dead time of L1 trigger system is reduced. The design can meet the need of L1 sub- trigger system.
Focused on the level 1 sub- trigger system in Silicon micro- strip array detector of the Cooling Storage Ring on the Heavy Ion Research Facility in Lanzhou( HIRFL- CSR),in this paper,based on the structural features of Xilinx 7 series FPGA chip,an improved design of logic circuit for the adder module is proposed,fast carry logic adder is employed and a new trigger judgment circuit is developed. Compared with the traditional adder circuit and the optimized,modeling analyses of structural performance and logic dead- time,the circuit was simulated and tested. The dead time of improved module is reduced to about 3 ns. Compared with other types of adder circuit structures,the signal processing time of new trigger judgment circuit is reduced,and the effective acquisition rate is increased,thus,the total dead time of L1 trigger system is reduced. The design can meet the need of L1 sub- trigger system.
引文
[1]Feng C Q,Liu S B,An Q.Electronics of BESIII TOF Monitor System[J].IEEE Transactions on Nuclear Science,2010,(57):463–466.
[2]Garvey J,Hillier S,Mahout G,et al.The ATLAS level-1 calorimeter trigger architecture[J].Nuclear Science,IEEE Transactions on Nuclear Science(512):2003,918-922.
[3]Bourrion O,Guernane R,Boyer B,et al.Level-1 jet trigger hardware for the ALICE electromagnetic calorimeter at LHC[J].Journal of Physics E:Scientific Instruments,2010,(5):12048–12048.
[4]DU Zhongwei,SU Hong,KONG Jie,et al.An improved technology for eliminating nondeterministic latency in the L1 trigger system[J].Nuclear Science and Techniques,2013,(24):020401.
[5]张惠国,王文锋,于宗光.FPGA快速进位链设计[J].常熟理工学报,2007,(8):75-79.
[2]Garvey J,Hillier S,Mahout G,et al.The ATLAS level-1 calorimeter trigger architecture[J].Nuclear Science,IEEE Transactions on Nuclear Science(512):2003,918-922.
[3]Bourrion O,Guernane R,Boyer B,et al.Level-1 jet trigger hardware for the ALICE electromagnetic calorimeter at LHC[J].Journal of Physics E:Scientific Instruments,2010,(5):12048–12048.
[4]DU Zhongwei,SU Hong,KONG Jie,et al.An improved technology for eliminating nondeterministic latency in the L1 trigger system[J].Nuclear Science and Techniques,2013,(24):020401.
[5]张惠国,王文锋,于宗光.FPGA快速进位链设计[J].常熟理工学报,2007,(8):75-79.