基于动态频率的芯片面积功耗优化设计
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摘要
芯片面积和功耗与工作频率紧密相关,在保持原有项目设计的条件下,利用门电路在不同频率下的开关工作原理,提出一种动态频率闭环设计方法,从系统级综合优化芯片的面积和功耗。通过筛选满足条件的多组测试集,建立频率与面积、频率与功耗的数学模型,综合考虑面积和功耗并计算出最优的频率。通过对一款已流片的芯片进行仿真验证,该方法同原有设计方法相比可以减少芯片面积约0.59%、降低功耗约9.01%。
Area and power consumption of an integrated circuit chip is strongly related to its operating frequency. Using the switching principle of the gate-level circuit under different frequencies and keeping the original design, a system level chip area and power consumption optimization method based on dynamic frequency adjustment is proposed in this paper. Firstly, the relationships of area vs. frequency and power consumption vs. frequency are established by choosing the multiple test sets which satisfy the restricting constraints. Secondly, the mathematical models of area vs. frequency and power consumption vs. frequency are derived.Then, the optimal operating frequency is obtained by resolving the models. With a tape out design, the proposed method achieved about 0. 59 % area shrink and about 9. 01 % reduction in power consumption.
Area and power consumption of an integrated circuit chip is strongly related to its operating frequency. Using the switching principle of the gate-level circuit under different frequencies and keeping the original design, a system level chip area and power consumption optimization method based on dynamic frequency adjustment is proposed in this paper. Firstly, the relationships of area vs. frequency and power consumption vs. frequency are established by choosing the multiple test sets which satisfy the restricting constraints. Secondly, the mathematical models of area vs. frequency and power consumption vs. frequency are derived.Then, the optimal operating frequency is obtained by resolving the models. With a tape out design, the proposed method achieved about 0. 59 % area shrink and about 9. 01 % reduction in power consumption.
引文
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[3]CHOURASIA A.Area optimized adder design using carry selection logic in power-constrained environments[J].International Journal of Engineering Innovation&Research,2017,6(1):48-50.
[4]MACII E,ZAFALON R.Low-power EDA technologies:state-of-the-art and beyond[C].2006 Advanced Signal Processing,Circuit and System Design Techniques for Communications.IEEE,2006:3-43.
[5]常晓涛,张志敏,王鑫.基于时钟树功耗预提取的SoC功耗估计方法[J].计算机工程,2006,32(1):234-236.
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