一种优化等离子体刻蚀工艺去静电步骤的方式
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摘要
该文研究并优化了等离子体刻蚀后、去静电过程中等离子体辅助晶片去静电的工艺步骤。通过数据模拟和实验设计,研究了极板间距、反应室压力、射频电源功率和射频电源关闭方式对晶片残存电荷的影响。首先,采用基于蒙特卡罗随机数方法的应用软件Pegasus对去静电过程中反应室内的等离子体分布进行了模拟,研究了等离子体能量分布图并分析了极板间距与等离子体分布均一性的关系,得到最佳极板间距范围。其次,以反应室压力、射频电源功率与极板间距为实验变量,通过实验设计得到残余电荷量最少的实验组。最后,以该实验组为基础,对射频电源的关闭方式进行优化,通过检测晶片脱离吸附装置时的电势差,得到最优射频电源关闭方式。该文研究结果可用于优化晶片去静电步骤,进而提高工艺可靠性和产品良率。
In this paper, the process steps of plasma-assisted wafer destaticization after plasma etching and destaticization were studied and optimized. Through the data simulation and experimental design, the effects of plate spacing, reaction chamber pressure, radio frequency(RF) power supply and RF power off mode on the residual charge of the wafer were studied. Firstly, the plasma distribution of the reaction chamber in the destaticization process was simulated by Monte Carlo random number method based on software Pegasus.The plasma energy distribution map was studied and the plate spacing and plasma distribution uniformity were analyzed. The relationship had been obtained with the best range of plate spacing. Secondly, the reaction chamber pressure, RF power and plate spacing were used as experimental variables, and the experimental group with the lowest residual charge was obtained through experimental design. Finally, based on the experimental group, the RF power supply shutdown mode was optimized. By detecting the potential difference when the wafer was detached from the adsorption device, the optimal RF power supply shutdown mode was obtained. The results of this paper could be used to optimize the wafer destaticization step and improve process reliability and product yield.
In this paper, the process steps of plasma-assisted wafer destaticization after plasma etching and destaticization were studied and optimized. Through the data simulation and experimental design, the effects of plate spacing, reaction chamber pressure, radio frequency(RF) power supply and RF power off mode on the residual charge of the wafer were studied. Firstly, the plasma distribution of the reaction chamber in the destaticization process was simulated by Monte Carlo random number method based on software Pegasus.The plasma energy distribution map was studied and the plate spacing and plasma distribution uniformity were analyzed. The relationship had been obtained with the best range of plate spacing. Secondly, the reaction chamber pressure, RF power and plate spacing were used as experimental variables, and the experimental group with the lowest residual charge was obtained through experimental design. Finally, based on the experimental group, the RF power supply shutdown mode was optimized. By detecting the potential difference when the wafer was detached from the adsorption device, the optimal RF power supply shutdown mode was obtained. The results of this paper could be used to optimize the wafer destaticization step and improve process reliability and product yield.
引文
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[2]张汝京,王志华.纳米集成电路制造工艺[M].北京:清华大学出版社,2015:162-164.
[3]Shama A,Blaga J,Agrawal S,et al.Optimization of wet clean and its cost effectiveness in dual Damascene 14 nm BEOL[C]//2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference(ASMC),2018:128-130.
[4]Lee J,Kim M,Lee J,et al.Study on defect reduction for high ratio etch process[C]//201728th Annual SEMI Advanced Semiconductor Manufacturing Conference(ASMC),2017,doi:10.1109/ASMC.2017.7969232.
[5]Gattere G,Rizzini F,Corso L,et al.Experiment investigation of mems DRIE etching dimensional loss[C]//2018 IEEE International Symposium on Inertial Sensors and Systems(INERTIAL),2018,doi:10.1109/ISISS.2018.8358123.
[6]Franz G,Averbeck R,Auer M,et al.Damage in III/V semiconductors caused by hard-and soft-etching plasmas[C]//2000 5th International Symposium on Plasma Process-Induced Damage,2000,doi:10.1109/PPID.2000.870644.
[7]Yang YM,Lim SW,Hong J,et al.Silicon trench etch uniformity improvement for microloading and macro-to-macro loading for sub 14 nm node[C]//2018 IEEE International Interconnect Technology Conference(IITC),2018:79-81.
[8]Ren J,Zhang HY,Zhang YY.SiN removal process for poly damage control in memory flash,[C]//2017 China Semiconductor Technology International Conference(CSTIC),2017,doi:10.1109/CSTIC.2017.7919790.