一种低失调高压大电流集成运算放大器
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摘要
基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。
A high voltage and high current operational power amplifier(HV-HC-OPA) with low offset voltage and current was proposed and verified based on junction field-effect-transistor(JFET) and bipolar junction transistor(BJT) compatible process.The input stage of the HV-HC-OPA is implemented by a p-JFET differential pair cascode structure.The middle stage uses BJTs as amplifiers and a compound active load structure is adopted.The output stage is composed of compound npn Darlington structure which can save a lot of chip area under the same output current compared to the traditional push-pull stage.The circuit was simulated and optimized based on Cadence Spectre simulator.Simulation results show that 95 dB voltage gain on 6 Ω load,0.224 5 mV input offset voltage,31.34 pA input bias current,3.3 pA input offset current and 9.6 MHz unity gain-bandwidth under ± 35 V double supply voltages.The maximum output peak current can reach 9 A.
A high voltage and high current operational power amplifier(HV-HC-OPA) with low offset voltage and current was proposed and verified based on junction field-effect-transistor(JFET) and bipolar junction transistor(BJT) compatible process.The input stage of the HV-HC-OPA is implemented by a p-JFET differential pair cascode structure.The middle stage uses BJTs as amplifiers and a compound active load structure is adopted.The output stage is composed of compound npn Darlington structure which can save a lot of chip area under the same output current compared to the traditional push-pull stage.The circuit was simulated and optimized based on Cadence Spectre simulator.Simulation results show that 95 dB voltage gain on 6 Ω load,0.224 5 mV input offset voltage,31.34 pA input bias current,3.3 pA input offset current and 9.6 MHz unity gain-bandwidth under ± 35 V double supply voltages.The maximum output peak current can reach 9 A.
引文
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[11]PROKOPENKO N N,PAKHOMOV I V,BUGAKOVAA V,et al.Zero level of Bi JFET-differential difference operational amplifiers and methods of its decrease in conditions of low temperatures and radiation effect[C]∥Proceedings of International Conference on Signals and Electronic Systems.Krakow,Poland,2016:131-134.
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[2]SHEU G,YANG M C,WU C Y.An innovated JFETstructure to adjust the pinch-off voltage by using a control gate[C]∥proceedings of International Conference on Electron Devices and Solid-State Circuits.Hsinchu,Taiwan,China,2017:1-2.
[3]薛晓磊,吴勃庆.一种含BJT缓冲级的高性能运算放大器的设计[J].通信电源技术,2017,34(04):161-162.XUE X L,WU B Q.Design of a high performance operational amplifier with BJT buffer[J].Telecom Power Technology,2017,34(04):161-162(in Chinese).
[4]李桂宏,谢世健.集成电路设计宝典[M].北京:电子工业出版社,2006:284.
[5]高华东,扈亦越,王丽雅.集成运放容性负载的瞬态响应分析及补偿[J].电子设计工程,2018,26(01):153-156.GAO H D,HU Y Y,WANG L Y.Performance analysis and compensation measures of operational amplifier circuit with capacitive load[J].Electronic Design Engineering,2018,26(01):153-156(in Chinese).
[6]何乐年,王忆.模拟集成电路设计与仿真[M].北京:科学出版社,2008:73-75.
[7]MAJD Y,SCD M,EBRAHIMI E.Low-power high-Gm quadrature LC-VCO using Darlington cell[C]∥Proceedings of Iranian Conference on Electrical Engineering.Mashhad,Iranian,2018:53-58.
[8]张明敏,王成鹤,杨阳,等.一款高性能JFET输入运算放大器[J].半导体技术,2018,43(02):115-119,135.ZHANG M M,WANG C H,YANG Y,et al.A high performance operational amplifier based on JFET-input[J].Semiconductor Technology,2018,43(02):115-119,135(in Chinese).
[9]郭飞.4H-SiC BJT功率器件特性与工艺研究[D].成都:电子科技大学,2017.
[10]PEI X J,CHEN Z,WANG S C,et al.Overcurrent protection for inverter-based distributed generation system[C]∥Proceedings of IEEE Energy Conversion Congress and Exposition.Montreal,QC,Canada,2015:2328-2332.
[11]PROKOPENKO N N,PAKHOMOV I V,BUGAKOVAA V,et al.Zero level of Bi JFET-differential difference operational amplifiers and methods of its decrease in conditions of low temperatures and radiation effect[C]∥Proceedings of International Conference on Signals and Electronic Systems.Krakow,Poland,2016:131-134.
[12]IVANOV V,BAUM D.A 3 A 20 MHz Bi CMOS/DMOSpower operational amplifier:a structural design approach[C]∥Proceedings of IEEE International Solid-State Circuits Conference.San Francisco,CA,USA,2003:138-141.