一款高性能JFET输入运算放大器
|
摘要
基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺设计了一种高性能运算放大器。电路设计采用了JFET作为运算放大器的输入级,实现了高输入阻抗和宽带宽,采用BJT实现了高的转换速率和高的可靠性。基于运算放大器工作原理的分析,对运算放大器的特性参数进行了仿真和优化,采用Bi-JFET工艺进行了工艺流片。测试结果表明,运算放大器在±15 V电源电压下输入失调电压为0.57 mV,输入偏置电流为0.021 nA,输入失调电流为0.003 nA,单位增益带宽为4.8 MHz,静态功耗为48 m W。运算放大器芯片版图尺寸为1.2 mm×1.0 mm。
A high performance operational amplifier was designed based on the junction field effect transistor( JFET) and bipolar junction transistor( BJT) compatible process. The circuit was designed using the JFET as the input stage of the operational amplifier to achieve high input impedance and wide bandwidth,and it also achieved high conversion rate and high reliability using BJT. Based on the analysis of operating principles of the operational amplifier,the characteristic parameters of the circuit were simulated and optimizated. The operational amplifier chip was fabricated using the Bi-JFET process. The test results show that with the supply voltage of ±15 V,the input offset voltage of the operation amplifier is 0. 57 mV,the input bias current is 0. 021 nA,the input offset current is 0. 003 nA,the unity-gain bandwidth is 4. 8 MHz,and the static power consumption is 48 m W. The chip layout area of the operational amplifier is 1. 2 mm×1. 0 mm.
A high performance operational amplifier was designed based on the junction field effect transistor( JFET) and bipolar junction transistor( BJT) compatible process. The circuit was designed using the JFET as the input stage of the operational amplifier to achieve high input impedance and wide bandwidth,and it also achieved high conversion rate and high reliability using BJT. Based on the analysis of operating principles of the operational amplifier,the characteristic parameters of the circuit were simulated and optimizated. The operational amplifier chip was fabricated using the Bi-JFET process. The test results show that with the supply voltage of ±15 V,the input offset voltage of the operation amplifier is 0. 57 mV,the input bias current is 0. 021 nA,the input offset current is 0. 003 nA,the unity-gain bandwidth is 4. 8 MHz,and the static power consumption is 48 m W. The chip layout area of the operational amplifier is 1. 2 mm×1. 0 mm.
引文
[1]PAKHOMOV I V,MEDVEDEV D V,BUGAKOVA A V,et al.The new architectures of the class AB differential stages for the high-speed CMOS-Bi JFET of the operational and differential difference amplifier of the sensor analog interfaces[C]∥Proceedings of International Siberian Conference on Control and Communications.Astana,Kazakhstan,2017:1-6.
[2]WANG Z K,TANG Z H,LIU Y,et al.Design and application of the high-voltage ultra-shallow junction PJFET[C]∥Proceedings of International Workshop on Junction Technology.Shanghai,China,2010:1-4.
[3]DON D,GARY D.JFET depletion in super junction devices[C]∥Proceedings of the 20thInternational Symposium on Power Semiconductor Devices and IC's.Orlando,FL,USA,2008:157-160.
[4]DURDAUT P,PENNER V,KIRCHHOF C,et al.Noise of a JFET charge amplifier for piezoelectric sensors[J].IEEE Sensors Journal,2017,17(22):7364-7371.
[5]PROKOPENKO N N,PAKHOMOV I V,BUGAKOVA A V,et al.Zero level of Bi JFET-differential difference operational amplifiers and methods of its decrease in conditions of low temperatures and radiation effect[C]∥Proceedings of International Conference on Signals and Electronic Systems.Krakow,Poland,2016:131-134.
[6]YANG T,LU J J,HOLLEMAN J.A high input impedance low-noise instrumentation amplifier with JFET input[C]∥Proceedings of the 56thIEEE International Midwest Symposium on Circuits and Systems.Columbus,OH,USA,2013:173-176.
[7]SNOEIJ M F,IVANOV M V.A 36 V JFET-input bipolar operational amplifier with 1μV/℃maximum offset drift and-126 d B total harmonic distortion[C]∥Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers.San Francisco,CA,USA,2011:248-250.
[8]TITOV A E,PROKOPENKO N N,ZHEBRUN E A,et al.The radiation-hardened instrumentation amplifier based on the differential difference operational amplifier for Bi JFET technological process[C]∥Proceedings of IEEE East-West Design&Test Symposium.Batumi,Georgia,2015:1-4.
[2]WANG Z K,TANG Z H,LIU Y,et al.Design and application of the high-voltage ultra-shallow junction PJFET[C]∥Proceedings of International Workshop on Junction Technology.Shanghai,China,2010:1-4.
[3]DON D,GARY D.JFET depletion in super junction devices[C]∥Proceedings of the 20thInternational Symposium on Power Semiconductor Devices and IC's.Orlando,FL,USA,2008:157-160.
[4]DURDAUT P,PENNER V,KIRCHHOF C,et al.Noise of a JFET charge amplifier for piezoelectric sensors[J].IEEE Sensors Journal,2017,17(22):7364-7371.
[5]PROKOPENKO N N,PAKHOMOV I V,BUGAKOVA A V,et al.Zero level of Bi JFET-differential difference operational amplifiers and methods of its decrease in conditions of low temperatures and radiation effect[C]∥Proceedings of International Conference on Signals and Electronic Systems.Krakow,Poland,2016:131-134.
[6]YANG T,LU J J,HOLLEMAN J.A high input impedance low-noise instrumentation amplifier with JFET input[C]∥Proceedings of the 56thIEEE International Midwest Symposium on Circuits and Systems.Columbus,OH,USA,2013:173-176.
[7]SNOEIJ M F,IVANOV M V.A 36 V JFET-input bipolar operational amplifier with 1μV/℃maximum offset drift and-126 d B total harmonic distortion[C]∥Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers.San Francisco,CA,USA,2011:248-250.
[8]TITOV A E,PROKOPENKO N N,ZHEBRUN E A,et al.The radiation-hardened instrumentation amplifier based on the differential difference operational amplifier for Bi JFET technological process[C]∥Proceedings of IEEE East-West Design&Test Symposium.Batumi,Georgia,2015:1-4.