针对RAM防护的二维多比特报警法
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摘要
针对安全芯片中RAM故障对系统安全性的危害,提出了一种基于二维纠错码的RAM防护技术,即二维多比特纠正报警法(TDMBAM)。该技术设计了一种可以有效识别、纠正RAM故障类型的二维纠错码,并可对二维纠错码的纠错能力和RAM的故障类型进行评估。TDMBAM对RAM进行了分区防护,将RAM分为程序存储区和数据存储区,并根据存储区的各自特点设计相异的纠错报警电路。对TDMBAM进行算法仿真,结果表明TDMBAM纠正了给定宽度内所有的连续和非连续故障,并对超过识别能力的故障给出了报警。报警后的系统有99.147 7%没有产生系统故障,并按照系统预定状态工作。
The two-dimensional multi-bits alarm method(TDMBAM) is proposed to reduce the damage of system security caused by RAM faults. The proposed method is based on two-dimensional error correction code.TDMBAM is able to correct multiple bit faults of RAM with any possible width and evaluate the error correcting capacity of two-dimensional code and RAM faults type. TDMBAM is designed to have partitioned protection for RAM with program memory block and data memory block, and has two different error correcting alarm circuits according to the respective characteristics of two memory blocks. TDMBAM is simulated and the results show that it is able to correct all continuous and discontinuous faults within the given width, and able to alarm faults beyond identification. Up to 99.147 7% alarmed systems are able to work in schedule without system faults.
The two-dimensional multi-bits alarm method(TDMBAM) is proposed to reduce the damage of system security caused by RAM faults. The proposed method is based on two-dimensional error correction code.TDMBAM is able to correct multiple bit faults of RAM with any possible width and evaluate the error correcting capacity of two-dimensional code and RAM faults type. TDMBAM is designed to have partitioned protection for RAM with program memory block and data memory block, and has two different error correcting alarm circuits according to the respective characteristics of two memory blocks. TDMBAM is simulated and the results show that it is able to correct all continuous and discontinuous faults within the given width, and able to alarm faults beyond identification. Up to 99.147 7% alarmed systems are able to work in schedule without system faults.
引文
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[6]PRAVEEN K S,JEREMY R,SRINIVAS K.Selective triple modular redundancy(STMR)based single-event upset(SEU)tolerant synthesis for FPGAs[J].IEEE Transactions on Nuclear Science,2004,51(5):2957-2969.
[7]PRAAT B,CAFFREY M,GRAHAM P,et al.Improving FPGA design robustness with partial TMR[C]//The 44th Reliability Physics Symposium.San Jose,California,USA:[s.n.],2006:26-30.
[8]MUKHERJEE S S,EMER J,FOSSUM T,et al.Cache scrubbing in microprocessors:Myth or necessity?[C]//The10th IEEE Pacific Rim International Symposium on Dependable Computing(PRDC’04).Papeete,Tahiti,French Polynesia:[s.n.],2004:3-5.
[9]AMD.BIOS and Kernel developer’s guide for AMD athlon64 and AMD opteron processors[EB/OL].[2017-08-17].http://go.microsoft.com/fwlink/?LinkId=28165.
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[11]DUBROVA E.Fault-tolerant design[M].New York:Springer,2013.
[12]ANDO H.High-performance energy-efficient microprocessor design[M].Netherlands:Springer,2006.
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[14]CARDARILLI G C,LEANDRI A,MARINUCCI P,et al.Design of a faulttolerant solid state mass memory[J].IEEETransactions on Reliability,2003,52(4):476-491.
[15]EBRAHIMI M,RAO P M B,SEYYEDI R,et al.Low-cost multiple bit upset correction in SRAM-based FPGAconfiguration frames[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems,2016,24(3):932-943.
[16]KIM J,HARDAVELLAS N,MAI K,et al.Multi-bit error tolerant caches using two-dimensional error coding[C]//The 40th Annual IEEE/ACM International Symposium on Microarchitecture.Cambridge,UK:[s.n.],2007:13-17.
[17]TIRI K,HWANG D.A side-channel leakage free coprocessor IC in 0.18μm CMOS for embedded AES-based cryptographic and biometric processing[C]//ACM/IEEE Design Automation Conference(DAC).[S.l.]:IEEE,2005:222-227.
[18]周永彬,徐秋亮.中国密码学发展报告2008[M].北京:电子工业出版社,2009.ZHOU Yong-bin,XU Qiu-liang.The development report of China cryptology 2008[M].Beijing:Publishing House of Electronics Industry,2009.
[19]YAO J,ZHANG T.Hardware/software co-design to secure cryptochip from side channel analysis at design time[C]//Proceedings of the 3rd IEEE International Conference on Computer Science and Information Technology(ICCSIT).[S.l.]:IEEE,2010,6:88-91.