GPU颜色单元压缩解压缩电路设计与实现
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摘要
图形处理器中颜色单元与片外DDR3存储器需要频繁地交换大量数据,与此同时DDR3存储器还要响应来自显示控制单元、深度单元、纹理单元的数据访问请求。为了优化DDR3访问带宽,颜色单元与DDR3存储器之间的压缩解压缩通路变得尤为重要。提出一种面向GPU颜色单元的压缩解压缩电路结构,采用ECPD算法,为GPU的颜色单元、显示控制单元与外部DDR3存储器之间提供颜色数据压缩解压缩通路。压缩电路将颜色单元写回的颜色数据进行压缩并存储至DDR3存储器,解压缩电路将从DDR3存储器读取回来的数据进行解压缩并提交给颜色单元或显示控制单元使用。基于虚拟仿真平台和Xilinx FPGA构成的原型系统对压缩解压缩电路进行了验证,结果表明压缩解压缩电路各项功能正确,实现了颜色单元、显示控制单元与DDR3存储器之间的流水操作。
In GPU,there are lots of data exchange between pixel cache and external DDR3 memory,meanwhile,the display control unit,depth unit and texture unit also request data access from DDR3 memory.In order to optimize the bandwidth of DDR3,the compression and decompression circuit between pixel cache and DDR3 memory becomes more and more important.This paper proposes a color compression and decompression circuit in GPU,which adopts ECPD algorithm,provides a route of color compress and decompress between pixel cache,display control unit and external DDR3 memory.The compression circuit packs the color data which was written back from pixel cache,stores the compressed data to DDR3 memory.The decompression circuit reads compressed data from DDR3 memory,unpacks it,and submits the decompressed data to pixel cache or display control unit.We design and implement the color compression and decompression circuit,and verify it based on virtual simulating platform and Xilinx FPGA prototype.The results indicate that the functions of the circuit are correct,and the pipeline operation between pixel cache,display control unit and DDR3 memory is realized.
In GPU,there are lots of data exchange between pixel cache and external DDR3 memory,meanwhile,the display control unit,depth unit and texture unit also request data access from DDR3 memory.In order to optimize the bandwidth of DDR3,the compression and decompression circuit between pixel cache and DDR3 memory becomes more and more important.This paper proposes a color compression and decompression circuit in GPU,which adopts ECPD algorithm,provides a route of color compress and decompress between pixel cache,display control unit and external DDR3 memory.The compression circuit packs the color data which was written back from pixel cache,stores the compressed data to DDR3 memory.The decompression circuit reads compressed data from DDR3 memory,unpacks it,and submits the decompressed data to pixel cache or display control unit.We design and implement the color compression and decompression circuit,and verify it based on virtual simulating platform and Xilinx FPGA prototype.The results indicate that the functions of the circuit are correct,and the pipeline operation between pixel cache,display control unit and DDR3 memory is realized.
引文
[1] Jim Rasmusson,Jon Hasselgren.Exact and Error- bounded Approximate Color Buffer Compression and Decompression[C].San Diego,California,USA:Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware,2007.
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[2] 韩立敏,田泽,张骏,等.图形处理器流水线数据压缩技术研究综述[J].计算机应用研究,2018,35(3):648-653.
[3] Timothy J Van Hook.Method and Apparatus for Compression and Decompression of Color Data.USA:7039241 B1[P].2006.
[4] Gordon M Elder.Method and Apparatus for Anti- Aliasing using Floating Point Subpixel Color Values and Compression of Same.USA:2006/0188161 A1[P].2006.
[5] Steven E Molnar,Bengt- Olaf Schneider,John Montrym,et al.System and Method for Real- Time Compressionof Pixel Colors.USA:6825847 B1[P].2004.
[6] Steven L Morein,Mark A Natale.System,Method,and Apparatus forCompression of Video Data using Offset Values.USA:2003/0038803 A1[P].2003.
[7] 顾文恺.基于GPU的脉冲压缩并行化研究[J].航空计算技术,2017,47(2):112-124,130.