基于ASL1000的Bandgap Trim 设计及其算法研究
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摘要
在芯片生产过程中,由于工艺的影响,带隙基准电压V_(BG)会存在偏差。在芯片测试阶段,需要对V_(BG)进行trim修调,使其满足芯片参数要求。简要分析了带隙基准电压误差的来源,提出了一种E-Fuse修调电路,通过程序中的代码控制修调电阻的大小,使V_(BG)满足要求。同时,在该修调电路的基础上,采用了一种新型算法,使得测试芯片V_(BG)的时间缩短了近558 ms,减少了测试时间,降低了测试成本。
In the process of chip production, bandgap reference voltage V_(BG)will produce deviation due to the influence of process. In the chip test phase, the V_(BG) was trimmed to meet the requirements of chip parameters. The deviation of bandgap reference voltage was analyzed briefly and a E-Fuse trim circuit was proposed. The size of resistance tolerance was controlled by the procedure of code, making V_(BG)meet requirements. At the same time, using a new algorithm on the basis of this trim circuit, the time of testing chip′s V_(BG)decreases nearly 558 ms, reducing test time and test cost.
In the process of chip production, bandgap reference voltage V_(BG)will produce deviation due to the influence of process. In the chip test phase, the V_(BG) was trimmed to meet the requirements of chip parameters. The deviation of bandgap reference voltage was analyzed briefly and a E-Fuse trim circuit was proposed. The size of resistance tolerance was controlled by the procedure of code, making V_(BG)meet requirements. At the same time, using a new algorithm on the basis of this trim circuit, the time of testing chip′s V_(BG)decreases nearly 558 ms, reducing test time and test cost.
引文
[1] 葛南,陈东坡. ATE测试中的Bandgap Trim技术研究[J]. 微电子学与计算机,2015(4):70-74.
[2] 汤华莲, 庄奕琪, 张丽,等. 一种可校准的低温漂基准电流源[J]. 西安电子科技大学学报, 2013,40(4):130-136.
[3] Gupta V. An Accurate, Trimless, High PSRR, Low-Voltage, CMOS Bandgap Reference IC[M]. Vishal Gupta: Georgia Institute of Technology, 2007: 1-33.
[4] Cao Y, Cock W D, Steyaert M, et al. A 4.5 MGy TID-tolerant CMOS bandgap reference circuit using a dynamic base leakage compensation technique[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2819-2824.
[5] Thomas D B, Najafizadeh L, Cressler J D, et al. Optimization of SiGe bandgap-based circuits for up to 300 °C operation[J]. Solid State Electronics, 2011, 56(1): 47-55.
[6] Betts W R. Analysis and design of analog integrated circuits[J]. Electronics & Power, 2009, 24(7): 533.
[7] Ning Zhihua. A low drift curvature-compensated bandgap reference with trimming resistive circuit[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(8): 698-706.
[2] 汤华莲, 庄奕琪, 张丽,等. 一种可校准的低温漂基准电流源[J]. 西安电子科技大学学报, 2013,40(4):130-136.
[3] Gupta V. An Accurate, Trimless, High PSRR, Low-Voltage, CMOS Bandgap Reference IC[M]. Vishal Gupta: Georgia Institute of Technology, 2007: 1-33.
[4] Cao Y, Cock W D, Steyaert M, et al. A 4.5 MGy TID-tolerant CMOS bandgap reference circuit using a dynamic base leakage compensation technique[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2819-2824.
[5] Thomas D B, Najafizadeh L, Cressler J D, et al. Optimization of SiGe bandgap-based circuits for up to 300 °C operation[J]. Solid State Electronics, 2011, 56(1): 47-55.
[6] Betts W R. Analysis and design of analog integrated circuits[J]. Electronics & Power, 2009, 24(7): 533.
[7] Ning Zhihua. A low drift curvature-compensated bandgap reference with trimming resistive circuit[J]. Frontiers of Information Technology & Electronic Engineering, 2011, 12(8): 698-706.