利用少数相关位的SoC测试数据压缩方法
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  • 英文篇名:Test data compression of system-on-chip (SoC) using few relevant bits
  • 作者:欧阳一鸣 ; 黄贵林 ; 梁华国 ; 谢涛 ; 黄正峰
  • 英文作者:Ouyang Yiming1 Huang Guilin1 Liang Huaguo2 Xie Tao1,3 Huang Zhengfeng2(1.School of Computer and Information,Hefei University of Technology,Hefei 230009,China;2.School of Electronic Science & Applied Physics,Hefei University of Technology,Hefei 230009,China;3.Department of Computer Science,San Diego State University,San Diego,CA92182,USA)
  • 关键词:相关位 ; 哈夫曼 ; 测试数据压缩
  • 英文关键词:relevant bits;Huffman;test data compression
  • 中文刊名:DZIY
  • 英文刊名:Journal of Electronic Measurement and Instrument
  • 机构:合肥工业大学计算机与信息学院;合肥工业大学电子科学与应用物理学院;美国圣地亚哥州立大学计算机科学系;
  • 出版日期:2013-01-15
  • 出版单位:电子测量与仪器学报
  • 年:2013
  • 期:v.27;No.145
  • 基金:国家自然科学基金(61274036、61106038);; 安徽高校省级自然科学研究重点(KJ2010A269);; 安徽省科技攻关(11010202190)资助项目
  • 语种:中文;
  • 页:DZIY201301019
  • 页数:7
  • CN:01
  • ISSN:11-2488/TN
  • 分类号:84-90
摘要
随着系统芯片集成度的提高,芯片所需要的测试数据也越来越庞大,为解决由此带来的自动测试设备(ATE)存储容量和带宽之间的矛盾,提出了一种基于数据块之间极少数相同位或极少数不同位的测试数据压缩及解压算法。根据数据块之间这些极少数相同位或极少数不同位,低频次数据块与参与Huffman编码的高频次数据块取得相关性联系,并通过一定的方式共享其较短的哈夫曼码字,从而精简Huffman编码状态表,达到测试数据压缩的目的。与同类经典方案相比,实验表明该方案的平均压缩率提高了6.11%~22.89%,且算法简单。
        With the improvement of ystem-on-chip integration,large amount of test data for the chip is required increasingly.To solve the contradiction between the storage capacity and bandwidth of automatic test equipment(ATE),a new method of test data compression/decompression is proposed based on few same or different bits between different blocks.Based on the low frequency data blocks associated with the high frequency data blocks which participated in the Huffman encoding by few same or different bits,and shared shorter Huffman codeword with them in a certain way,thereby the state table of Huffman coding could be simplified and the purpose of test data compression is reached.According to the experimental results,the compression ratio increases by 6.11% to 22.89% compared with that of other schemes,and also the proposed method is simple.
引文
[1]MOORE G.Progress in Digital Integrated Electronics[C].Proceedings of International Electron Device Meeting(IEDM)Teeh.Digest,1975:11-13.
    [2]TOUBA N A.Survey of test vector compression techniques[J].IEEE Des.Test Comput,2006,23(4):294-303.
    [3]KOENEMANN B.LFSR-coded test patterns for scan de-signs[C].Proceedings of European Test Conference,Mu-nich,Germany,1991:237-242.
    [4]YI M X,LI H G,ZHAN K Z,et al.Optimal LFSR-codingtest data compression based on test cube dividing[C].Pro-ceeding of International Conference on ComputationalScience and Engineering,2009:698-702.
    [5]MITRA S,KIM K S.XPAND:an efficient test stimuluscompression technique[J].IEEE Transaction on Com-puters,2006,55(2):163-173.
    [6]俞洋,彭喜元,张毅刚.基于重复子向量的测试数据压缩算法[J].仪器仪表学报,2009,30(2):356-361.YU Y,PENG X Y,ZHANG Y G.Test data compressionmethod for multiple scan chains based on repeatedsub-vectors[J].Chinese Journal of Scientific Instrument,2009,30(2):356-361.
    [7]ANSHUMAN C,KRISHNENDU C.Test data compressionand decompression based on internal scan chains and Golombcoding[J].IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems,2002,21(6):715-722.
    [8]ANSHUMAN C,KRISHNENDU C.Test data compres-sion and test resource partitioning for system-on-a-chip us-ing frequency-directed run-length(FDR)codes[J].IEEETransactions on Computers,2003,52(8):1076-1088.
    [9]CHANDRA A,CHAKRABARTY K.A unified approachto reduce SoC test data volume,scan power and testingtime[J].IEEE Transaction on.Computer-Aided DesignIntegrated Circuits Syst.,2003,22(3):352-363.
    [10]EL-MALEH A H,AL-ABAJI R H.Extended frequency-directed run length code with improved application to sys-tem-on-a-chip test data compression[C].Proceeding of 9thIEEE Int.Conference Electronic,Circuits System,2002:449-452.
    [11]NOURANI M,TEHRANIPOUR M.RL-Huffman encod-ing for test compression and power reduction in scan ap-plication[J].ACM Trans.Des.Autom.Electron.Syst.,2005,10(1):91-115.
    [12]TEHRANIPOOR M,NOURANI M,CHAKRABARTYK.Nine-coded compression technique for testing embed-ded cores in SoCs[J].IEEE Trans.VLSI Systems,2005,13(6):719-731.
    [13]EL-MALEH A H.Efficient test compression techniquebased on block merging[J].IET Computer Digital Tech-nology,2008,2(5):327-335.
    [14]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压[J].计算机学报,2004,27(4):549-554.LIANG H G,JIANG C Y.Efficient test data compression anddecompression based on alternation and run length codes[J].Chinese Journal of Computers,2004,27(4):549-554.
    [15]GONCIARI P T,AL-HASHIMI B,NICOLICI N.Im-proving compression ratio,area overhead,and test appli-cation time for system-on-a-chip test data compres-sion/decompression[C].Proceeding of Design Automa-tion Test in Europe,Paris,France,2002:604-611.
    [16]欧阳一鸣,邹宝升,梁华国,等.基于部分游程翻转的SoC测试数据压缩[J].电子测量与仪器学报,2010,24(1):23-28.OUYANG Y M,ZOU B SH,LIANG H G,et al.Test datacompression of system-on-a-chip(SoC)based on partialruns reversing[J].Journal of Electronic Measurement andInstrument,2010,24(1):23-28.
    [17]胡兵,陈光礻禹,谢永乐.基于变移霍夫曼编码的SOC测试数据压缩[J].仪器仪表学报,2005,26(11):1114-1118.HU B,CHEN G J,XIE Y L.System-on-a-chip test datacompression based on Huffman shift codes[J].ChineseJournal of Scientific Instrument,2005,26(11):1114-1118.
    [18]JAS A,GHOSH-DASTIDAR J,MOM-ENG N G,et al.An efficient test vector compression scheme using selec-tive Huffman coding[J].IEEE Transaction on.Computer-Aided Design of Integrated Circuits and Systems,2003,22,(6):797-806.
    [19]KAVOUSIANOS X,KALLIGEROS E,NIKOLOS D.Optimal selective Huffman coding for test-data compres-sion[J].IEEE Transaction on.Computers,2007,56(8):1146-1152.

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