一种具有上电启动功能的差分环形压控振荡器
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摘要
设计了一种具有上电启动功能的差分环形压控振荡器(VCO),该电路可作为时钟产生模块应用于SoC中的高速锁相环(PLL)。该VCO采用全差分延迟结构,可更好地抑制来自电源的共模噪声。增加了使控制电压变化可控的上电启动电路,便于控制PLL中环路开启次序,缩短PLL锁定时间,为延迟单元提供适当的初始偏置和起振条件。基于GF 28 nm标准CMOS工艺进行电路设计、仿真和版图设计。仿真结果表明,该VCO具有良好的起振可靠性和稳定性,输出频率调谐范围为0.65～3.9 GHz。在1 V电源电压、1.625 GHz中心频率时,相位噪声为-80.44 dBc/Hz@1 MHz,功耗为6.6 mW。应用该VCO的PLL的测试结果表明,锁定时间为1.6μs,频率调谐范围和锁定时间均优于对比文献。
A differential ring voltage controlled oscillator(VCO) with power-on start function was designed, which was used as a clock generation module for the applications of high speed phase locked loops(PLL) in SoC. A fully differential delay structure was used to suppress the common mode noise from the power supply. To ensure the control voltage variation of the VCO was controllable, a power-on starting circuit was incorporated, so as to control the opening sequences of the loop, to shorten the lock time of the PLL, and to provide an appropriate initial offset and starting conditions for delay unit. Circuit design, simulation and layout design were based on GF 28 nm standard CMOS process. The simulation results showed that the proposed VCO had an excellent start-up reliability and stability, and the tuning range of output frequency was 0.65～3.9 GHz. The phase noise was-80.44 dBc/Hz@1 MHz, and the power consumption was 6.6 mW under 1.0 V power supply and 1.625 GHz center frequency. The PLL with the proposed VCO had a lock time of 1.6 μs. The frequency tuning range and lock time of the VCO were superior to the referred literatures.
A differential ring voltage controlled oscillator(VCO) with power-on start function was designed, which was used as a clock generation module for the applications of high speed phase locked loops(PLL) in SoC. A fully differential delay structure was used to suppress the common mode noise from the power supply. To ensure the control voltage variation of the VCO was controllable, a power-on starting circuit was incorporated, so as to control the opening sequences of the loop, to shorten the lock time of the PLL, and to provide an appropriate initial offset and starting conditions for delay unit. Circuit design, simulation and layout design were based on GF 28 nm standard CMOS process. The simulation results showed that the proposed VCO had an excellent start-up reliability and stability, and the tuning range of output frequency was 0.65～3.9 GHz. The phase noise was-80.44 dBc/Hz@1 MHz, and the power consumption was 6.6 mW under 1.0 V power supply and 1.625 GHz center frequency. The PLL with the proposed VCO had a lock time of 1.6 μs. The frequency tuning range and lock time of the VCO were superior to the referred literatures.
引文
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[2] KHACHIKYAN K,MSRYAN L,BALABANYAN A,et al.Research of PVT variation influence on PLL system and methodology of control voltage stabilization [C] // IEEE 37th Int Conf Elec & Nanotechnol.Kiev,Ukraine.2017:190-193.
[3] 谷银川,黄鲁,张步青.一种全差分双路延迟环形VCO的设计 [J].微电子学,2015,45(6):747-750.
[4] 王雪艳,朱恩,熊明珍,等.11 GHz CMOS环形压控振荡器设计 [J].半导体学报,2005,26(1):187-191.
[5] 童诗白,华成英.模拟电子技术基础 [M].北京:高等教育出版社,2012:293-302.
[6] 王镇道,伍锡安,朱小莉.一种新型低压低功耗伪差分环形压控振荡器设计 [J].湖南大学学报,2017,44(10):117-122.
[7] 桑红石,方海涛,余萌,等.环形振荡器对称负载特性分析 [J].微电子学与计算机,2011,28(5):197-200.
[8] 张辉,杨海钢,周发标,等.偶数级差分环形振荡器的稳定平衡态分析 [J].电子与信息学报,2011,33(8):1969-1974.
[9] GOEL A,TOMAR A,KUMAR N,et al.Low phase noise high switching ring VCO with quadrature output [C] // APMC.New Delhi,India.2016:1-3.
[10] 房军梁,张长春,陈德媛,等.一种新颖的正交输出伪差分环形VCO的设计 [J].南京邮电大学学报(自然科学版),2014,34(2):100-104.
[11] 耿晓勇,何惊昱,杨建红.无晶振快速锁定高精度锁相环设计 [J].电子技术应用,2013,39(3):44-46.
[12] KUO K C,WU C W.An fast lock technique for wide band PLL frequency synthesizer design [C] // ISEEE.Sapporo,Japan.2014:759-763.
[13] CHIU W H,HUANG Y H,LIN T H.A dynamic phase error compensation technique for fast-locking phase-locked loops [J].IEEE J Sol Sta Circ,2010,45(6):1137-1149.