55nm双大马士革结构中电镀铜添加剂的研究
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摘要
本文研究了电镀铜过程中添加剂对55nm技术代双大马士革结构的影响,为集成电路制造生产线提供有力的数据支持.在12英寸电镀设备上,对不同添加剂配比所电镀的铜膜,分别进行了光片上的基本工艺性能、图形片上的填充性能、55nm技术代的铜互连工艺上的电学性能和可靠性的验证评估.通过对各种性能指标的考核,提出了针对该电镀液及添加剂的改进方案并优化电镀工艺菜单.最终确立其适用于芯片铜互连电镀工艺的工程应用窗口,使该产品满足集成电路制造生产线的要求.
In this paper,the influence of additives on the performance of Dual Damascene with the 55 nm technology during copper electroplating was studied,which provided strong support for the IC manufacturing.In the 12-inch plating equipment,the copper films electroplated with different additives were respectively subjected to the basic process performance on the blank wafer,the filling performance on the pattern wafer,and the electrical performance and reliability of the copper interconnect technology for 55 nm technology node.Through the assessment of various performance indicators,the improvement scheme for the electroplating solution and additives was proposed and the electroplating process was optimized.Finally,the engineering application window of the electroplating process for chip copper interconnect was confirmed,so that it met the requirements of the IC manufacturing production line.
In this paper,the influence of additives on the performance of Dual Damascene with the 55 nm technology during copper electroplating was studied,which provided strong support for the IC manufacturing.In the 12-inch plating equipment,the copper films electroplated with different additives were respectively subjected to the basic process performance on the blank wafer,the filling performance on the pattern wafer,and the electrical performance and reliability of the copper interconnect technology for 55 nm technology node.Through the assessment of various performance indicators,the improvement scheme for the electroplating solution and additives was proposed and the electroplating process was optimized.Finally,the engineering application window of the electroplating process for chip copper interconnect was confirmed,so that it met the requirements of the IC manufacturing production line.
引文
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[5]ZIELINSKI E M,RUSSELL S W,LIST R S.Damascene integration of copper and ultra-low-k xerogel for high performance interconnects[C]∥International Electron Devices Meeting,IEDM.December 10,1997,Washington,DC:IEEE,1997:936-938.
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[7]TAN M,HARB J N.Additive behavior during copper electrodeposition in solutions containing Cl-,PEG,and SPS[J].Journal of the Electrochemical Society,2003,150(6):415-20.
[8]MOHAN S,RAJ V.The effect of additives on the pulsed electrodeposition of copper[J].Transactions of the Imf,2005,83(4):194-198.
[2]ANDRICACOS P C.Copper on-chip interconnections—A breakthrough in electrodeposition to make better chips[J].Electrochem Soc Interface,1999,8(1):32-37.
[3]SIMPSON C,SPARKS T,TSUI P,et al.A high performance 1.8V,0.20μm CMOS technology with copper metallization[C]∥International Electron Devices Meeting,IEDM.December 10,1997,Washington,DC:IEEE,1997:769-772.
[4]EDELSTEIN D,HEIDENRICH J,GOLDBLATT R,et al.Full copper wiring in a sub-0.25/spl mu/m CMOS ULSI technology[C]∥International Electron Devices Meeting,IEDM.December 10,1997,Washington,DC:IEEE,1997:773-776.
[5]ZIELINSKI E M,RUSSELL S W,LIST R S.Damascene integration of copper and ultra-low-k xerogel for high performance interconnects[C]∥International Electron Devices Meeting,IEDM.December 10,1997,Washington,DC:IEEE,1997:936-938.
[6]WIESNER H J,FREY W P.Somemechanical-properties of copper electrodeposited from pyrophosphate and sulfate-solutions[J].Plat Surf Finish,1979,66(3):51-56.
[7]TAN M,HARB J N.Additive behavior during copper electrodeposition in solutions containing Cl-,PEG,and SPS[J].Journal of the Electrochemical Society,2003,150(6):415-20.
[8]MOHAN S,RAJ V.The effect of additives on the pulsed electrodeposition of copper[J].Transactions of the Imf,2005,83(4):194-198.