静电放电器件充电模型CDM失效机理分析
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摘要
CMOS集成电路进入纳米时代,电路的功能日趋复杂,面积也不断增加,电路自身存储的静电电荷对电路造成的损伤将不可忽视,在失效分析中,这种失效模型称为器件充电模型。详细介绍了器件充电模型与人体模型及机器模型在电路原理和电流波形上的不同之处,分析电路上存储电荷的机理和原因,主要是由于电路在生产和使用环境中受到静电源的感应以及电路和其他物体或空气的摩擦等造成。详细分析器件充电模型引起电路损伤的失效机理,器件充电模型作为一个电荷驱动型,其电流方向主要是由电路内部向外部流动,其电流大、上升速度快,会对电路的栅极造成损伤。
In nano-scale CMOS process, integrate circuit's area become larger, and it's function complicated. Because device's stored charges make device failed,which should be taken into consideration. This failure model is charged device model. The paper introduces the difference of circuit diagram and electric current between the human body model, the machine model and the charged device model. It explains the mechanism and the reasons how the device stored charges: in processes of the ICs, charges can be induced by the ESD source and device rub with other substances and air. Finally, it analysis the failure mechanism made by CDM. CDM is driven by charges, the direction of the ESD current is from device's inner to outer, it's high current and quick rise time will make the oxygen gate fail.
In nano-scale CMOS process, integrate circuit's area become larger, and it's function complicated. Because device's stored charges make device failed,which should be taken into consideration. This failure model is charged device model. The paper introduces the difference of circuit diagram and electric current between the human body model, the machine model and the charged device model. It explains the mechanism and the reasons how the device stored charges: in processes of the ICs, charges can be induced by the ESD source and device rub with other substances and air. Finally, it analysis the failure mechanism made by CDM. CDM is driven by charges, the direction of the ESD current is from device's inner to outer, it's high current and quick rise time will make the oxygen gate fail.
引文
[1]Steven H Voldman.ESD:Physics and Devices[M].John Wiley&Sons,Ltd,2004.
[2]Steven H Voldman.ESD:Failure Mechanisms and Models[M].John Wiley&Sons,Ltd,2004.
[3]Alburt Z H Wang.On chip protectiong for integrate circuits[C].Illinois Institute of Technology,2002.
[4]Jerry Soden,Jaume Segura,Charles F Hawkins.Electronics and Failure Analysis[C].Sandia National Labs,2011.
[2]Steven H Voldman.ESD:Failure Mechanisms and Models[M].John Wiley&Sons,Ltd,2004.
[3]Alburt Z H Wang.On chip protectiong for integrate circuits[C].Illinois Institute of Technology,2002.
[4]Jerry Soden,Jaume Segura,Charles F Hawkins.Electronics and Failure Analysis[C].Sandia National Labs,2011.