3200 Mbps DDR4 PHY的物理设计优化
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摘要
以一款基于TSMC 16nm FinFET工艺的HPC(High Performance Computing)芯片中DDR4PHY模块为研究对象,提出了其物理设计及优化方案,完成了DDR4PHY的布图规划和布局、时钟树综合与优化和时序收敛分析.布图规划时考虑到宏单元和IO单元的特性再结合面积和时序等性能的优化确定了DDR4PHY的布局形状.时钟树综合时,对比分析了传统的时钟树综合CTS和优化设计过的多源时钟树综合MSCTS,设计了针对DDR4PHY模块特点的大型多位缓冲器M2M8,其驱动距离可以达到1200μm.仿真实验结果表明,优化后的时钟树结构级数从65级降到19级,时钟最大延迟最多降低了48.37%,时钟偏差减少了52.33%,功耗降低了17.24%,DDR4PHY的各项性能优化结果显著,达到实验目的.
The physical design and its optimization were proposed for the DDR4 PHY of one High Performance Computing chip based on TSMC 16 nm FinFET process technology,including the floorplan、placement、clock tree synthesis and its optimization and timing closure analysis.Take macros and IO cells combined with area and timing optimization into account to fix the floorplan shape of DDR4 PHY.Compare the typical CTS with optimized MSCTS and analyze their differences when clock tree synthesis.Design multi-bit buffer M2 M8 for DDR4 PHY whose drive distance can be 1200μm.Simulation results show that optimized clock tree structure level decreases from 65 to 19,max clock latency decreases by 48.37%,clock skew decreases by 52.33%,power decreases by 17.24%,the performance optimization results are prominent and achieve the goal of experiment.
The physical design and its optimization were proposed for the DDR4 PHY of one High Performance Computing chip based on TSMC 16 nm FinFET process technology,including the floorplan、placement、clock tree synthesis and its optimization and timing closure analysis.Take macros and IO cells combined with area and timing optimization into account to fix the floorplan shape of DDR4 PHY.Compare the typical CTS with optimized MSCTS and analyze their differences when clock tree synthesis.Design multi-bit buffer M2 M8 for DDR4 PHY whose drive distance can be 1200μm.Simulation results show that optimized clock tree structure level decreases from 65 to 19,max clock latency decreases by 48.37%,clock skew decreases by 52.33%,power decreases by 17.24%,the performance optimization results are prominent and achieve the goal of experiment.
引文
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[2]SYNOPSYS.DDR4/3PHY for TSMC16FFPGL18Databook[R].CA,USA:Synopsys,2017.
[3]EWETZ,RICKARD,JANARTHANAN Shankarshana,KOH CHENG-KOK.Construction of reconfigurable clock trees for MCMM designs[C]//Proceedings of the 52nd Annual Design Automation Conference.San Francisco,CA,USA:ACM,2015:1-6.
[4]SYNOPSYS.IC CompilerⅡ:Block-level Implementation Workshop Student Guide:version 2017.09-SP2[R].CA,USA:Synopsys,2017.
[5]张玲,王澧.百万门系统级芯片的时钟树设计[J].电子与封装,2014,14(12):30-35.
[6]DONG-JIN LEE,IGOR L Markov.Multilevel tree fusion for robust clock networks[C]//ICCAD.San Jose,CA,USA:IEEE,2011:632-639.
[7]SHMUEL WIMER.Optimal weight allocation in rooted trees[J].Combinatorial Optimization,2016,31(3):1023-1033.
[8]KIM J,KIM T.Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs[C]//ASP-DAC.Tokyo,JP:IEEE,2015:466-471.
[9]LIN M P H,HSU C C,Chen Y C.Clock-tree aware multibit flip flop generation during placement for power optimization[J].IEEE Transactions on ComputerAided Design of Integrated Circuits System,2015,34(2):280-292.
[10]HOU W,LIU D,HOP H.Automatic register banking for low-power clock trees[C]//ISQED.San Jose,CA,USA:IEEE,2009:645-655.
[11]GUPTA S.LPDDR4X(3732 Mbps)DBI impact on SI/PI and power[C]//IEEE 26th Conference on EPEPS.San Jose,CA,USA:IEEE,2017:365-368.