基于层次化重复单元的FPGA结构描述方法
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摘要
针对具有多种逻辑块和互连线结构的现代主流现场可编程门阵列(FPGA),给出一种通用的FPGA结构描述方法。根据FPGA硬件版图由几类重复单元在水平和垂直方向复制拼接而成的特点,提出基于层次化重复单元的FPGA结构模型,在该模型的基础上,通过定义一套完整的语法来描述FPGA。实验结果表明,该方法能正确描述FPGA硬件信息,并配合FPGA软件系统正常工作,具有结构通用和描述文件小的优点。
Aiming at modern mainstream Field Programmable Gate Array(FPGA) with diverse logic blocks and interconnect lines,this paper proposes a universe FPGA architecture description method.Considering the fact that tiles are actually copied and pieced together to form the overall FPGA hardware layout,this paper proposes an FPGA architecture model based on hierarchical tile.According to the model,this paper also defines a set of complete and detailed syntactic rules to describe the FPGA architecture.Experimental results show that the description method can delineate FPGA hardware information,and work correctly with FPGA software system.It has common architecture and is small in size.
Aiming at modern mainstream Field Programmable Gate Array(FPGA) with diverse logic blocks and interconnect lines,this paper proposes a universe FPGA architecture description method.Considering the fact that tiles are actually copied and pieced together to form the overall FPGA hardware layout,this paper proposes an FPGA architecture model based on hierarchical tile.According to the model,this paper also defines a set of complete and detailed syntactic rules to describe the FPGA architecture.Experimental results show that the description method can delineate FPGA hardware information,and work correctly with FPGA software system.It has common architecture and is small in size.
引文
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[2]Betz V,Rose J,Marquardt A.Architecture and CAD for Deep-submicron FPGAs[M].London,UK:Kluwer Academic Publishers,1999.
[3]Cronquist D C,McMurchie L.Emerald——An Architecturedriven Tool Compiler for FPGA[C]//Proceedings of the 4th ACM International Symposium on Field-program Gate Arrays.New York,USA:ACM Press,1996:144-150.
[4]Betz V.VPR and T-Vpack User’s Manual[EB/OL].[2012-04-16].http://www.eecg.toronto/vpr/.
[5]Beckhoff C,Koch D.The Xilinx Design Language:Tutorial and Use Cases[C]//Proceedings of the 6th International Workshop on Reconfigurable Communicationcentric Systemson-Chip.Montpellier,France:[s.n.],2011:1-8.
[6]Wu Fang.A Delay-optimized Universal FPGA Routing Architecture[C]//Proceedings of 2009 Asia and South Pacific Design Automation Conference.Yokohama,Japan:[s.n.],2009:15-16.
[7]谢丁,来金梅.现代层次化可编程逻辑器件软件系统FDE2009[J].电子学报,2010,34(5):1136-1140.
[8]马珂洁,包杰,周学功,等.基于局部重配置的FPGA互连测试诊断[J].计算机工程,2011,37(5):249-252.