一种高速嵌套CRC码的生成方法及其FPGA实现
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摘要
为了实现高速融合网络数据传输中的差错控制,针对现有循环冗余校验码(CRC)计算速度难以进一步提升的问题,提出了一种用嵌套CRC码实现高速数据差错控制的方法,并在Xilinx公司的FPGA芯片上进行了实现。该嵌套CRC码由多个通道的传统CRC码并行计算器同步计算得到,可大幅度提升差错控制码的生成速度,并通过不同计算通道的组合,支持多种流量的差错控制。最后分析了嵌套CRC码的计算性能以及差错控制能力,并提供了设定嵌套次数、通道数以及计算通道并行计算位数的依据。
To achieve the data error control in high-speed converged network data transmission,a nested CRC code generation method was proposed to improve the situation that it is difficult to further enhance the computing speed through currently available cyclic redundancy check(CRC)code calculation technique.It was implemented on Xilinx Field Programmable Gate Array(FPGA)chip.This nested CRC code is obtained through calculating the traditional CRC code concurrently in multiple channels,and thus the speed of error control code generation is highly increased while multiple-types of data flows are processed by different kinds of calculating channels.At the end,the calculating performance and error control capability were analyzed and a guidance to set the nested level,the number of computing channel and parallel computing width of a single computing channel was given.
To achieve the data error control in high-speed converged network data transmission,a nested CRC code generation method was proposed to improve the situation that it is difficult to further enhance the computing speed through currently available cyclic redundancy check(CRC)code calculation technique.It was implemented on Xilinx Field Programmable Gate Array(FPGA)chip.This nested CRC code is obtained through calculating the traditional CRC code concurrently in multiple channels,and thus the speed of error control code generation is highly increased while multiple-types of data flows are processed by different kinds of calculating channels.At the end,the calculating performance and error control capability were analyzed and a guidance to set the nested level,the number of computing channel and parallel computing width of a single computing channel was given.
引文
[1]路渭华.下一代以太网发展趋势[J].光通信技术,2007,12:7-9
[2]Gai S,DeSanti C.思科数据中心I/O整合[M].陈柳,译.北京:邮电出版社,2013:2-12
[3]彭建辉.10G以太网接口并行CRC校验的一种简化算法[J].微计算机信息,2006,20:213-215
[4]Renuka H K,Jayashree C N.Design and Computation of Cyclic Redundancy Code for Ethernet Application:an Implementation Using FPGA[J].World Journal of Science and Technology,2011,1(8):68-73
[5]杨梅娟,尹德春.CRC算法的研究[J].计算机与数字工程,2005,34:30-32
[6]Kounavis M E,Berry F L.Novel Table Lookup-Based Algorithms for High-Performance CRC Generation[J].IEEE Trans.on Computer Society,2008,57(11):1550-1560
[7]梁海华,盘丽娜,赵秀兰,等.CRC查询表及其并行矩阵生成方法[J].计算机科学,2012,39(B06):154-158
[8]岳天天.一种并行CRC校验算法的IP设计与实现[J].广东通信技术,2013(3):78-79
[9]Sprachmann M.Automatic Generation of Parallel CRC Circuits[J].IEEE Design&Test of Computers,2001,18(3)
[10]俞迅.32位CRC校验码的并行算法及硬件实现[J].信息技术,2007(4):71-74
[11]廖海红.通信系统中的CRC算法的研究和工程实现[D].北京:北京邮电大学,2006:60-65
[12]徐展琦,裴昌幸,董淮南.一种通用多通道并行CRC计算及其实现[J].南京邮电大学学报:自然科学版,2008(2):53-57
[2]Gai S,DeSanti C.思科数据中心I/O整合[M].陈柳,译.北京:邮电出版社,2013:2-12
[3]彭建辉.10G以太网接口并行CRC校验的一种简化算法[J].微计算机信息,2006,20:213-215
[4]Renuka H K,Jayashree C N.Design and Computation of Cyclic Redundancy Code for Ethernet Application:an Implementation Using FPGA[J].World Journal of Science and Technology,2011,1(8):68-73
[5]杨梅娟,尹德春.CRC算法的研究[J].计算机与数字工程,2005,34:30-32
[6]Kounavis M E,Berry F L.Novel Table Lookup-Based Algorithms for High-Performance CRC Generation[J].IEEE Trans.on Computer Society,2008,57(11):1550-1560
[7]梁海华,盘丽娜,赵秀兰,等.CRC查询表及其并行矩阵生成方法[J].计算机科学,2012,39(B06):154-158
[8]岳天天.一种并行CRC校验算法的IP设计与实现[J].广东通信技术,2013(3):78-79
[9]Sprachmann M.Automatic Generation of Parallel CRC Circuits[J].IEEE Design&Test of Computers,2001,18(3)
[10]俞迅.32位CRC校验码的并行算法及硬件实现[J].信息技术,2007(4):71-74
[11]廖海红.通信系统中的CRC算法的研究和工程实现[D].北京:北京邮电大学,2006:60-65
[12]徐展琦,裴昌幸,董淮南.一种通用多通道并行CRC计算及其实现[J].南京邮电大学学报:自然科学版,2008(2):53-57