三维片上网络正四面体裂变拓扑结构研究
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摘要
旨在研究新型三维片上网络正四面体裂变拓扑结构,给出了该拓扑结构的生成过程;对该拓扑结构进行了编码设计和路由设计。通过对gpNoCsim片上网络仿真器进行三维扩展,对正四面体裂变拓扑结构进行性能仿真实验。仿真结果表明,在均匀负载模式下,正四面体裂变拓扑结构的平均延时和平均跳数均低于Mesh结构,当注入率为0. 02时,平均延时比Mesh结构低16. 8%、平均跳数比Mesh结构少5. 5%;在局部负载模式下,当注入率大于0. 008时,正四面体裂变拓扑结构的平均延时和平均跳数与Mesh结构相比均有明显改善;当注入率为0. 014时,平均延时比Mesh结构降低18. 7%、平均跳数比Mesh结构减少9. 6%。这说明正四面体裂变拓扑结构可用于三维片上网络拓扑结构设计。
This paper aimed to research the tetrahedron fission topology that was a new type of three dimensional network-onchip topology,it gave generation process of topology and the design of encoding and routing. Through a three dimensional extension of the gpNoCsim which was a simulator on chip network,this paper conducted the simulation experiment of the tetrahedron fission topology. The simulation results show,tetrahedron fission topology can achieve lower average latency and fewer average hops than Mesh under uniform traffic pattern,when the injection rate is 0. 02,comparing with Mesh,the average latency degrades by 16. 8% and the average hops decrease 5. 5%. Under localized traffic pattern,the average delay of tetrahedral fission topology and the average hops are significantly improved when the injection rate is greater than 0. 008,compared with Mesh,tetrahedron fission leads to 18. 7% decrease of the average latency and 9. 6% decrease of the average hops when the injection rate is 0. 014. It shows that the tetrahedron fission topology can be used in the design of three dimensional network-on-chip topology.
This paper aimed to research the tetrahedron fission topology that was a new type of three dimensional network-onchip topology,it gave generation process of topology and the design of encoding and routing. Through a three dimensional extension of the gpNoCsim which was a simulator on chip network,this paper conducted the simulation experiment of the tetrahedron fission topology. The simulation results show,tetrahedron fission topology can achieve lower average latency and fewer average hops than Mesh under uniform traffic pattern,when the injection rate is 0. 02,comparing with Mesh,the average latency degrades by 16. 8% and the average hops decrease 5. 5%. Under localized traffic pattern,the average delay of tetrahedral fission topology and the average hops are significantly improved when the injection rate is greater than 0. 008,compared with Mesh,tetrahedron fission leads to 18. 7% decrease of the average latency and 9. 6% decrease of the average hops when the injection rate is 0. 014. It shows that the tetrahedron fission topology can be used in the design of three dimensional network-on-chip topology.
引文
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[3] Lee D,Das S,Pande P P. Performance-thermal trade-offs for a VFIenabled 3D No C architecture[C]//Proc of International Symposium on Quality Electronic Design. Piscataway,NJ:IEEE Press,2017:271-276.
[4] Rezaei S H S,Modarressi M,Daneshtalab M,et al. A three dimensional networks-on-chip architecture with dynamic buffer sharing[C]//Proc of Euromicro International Conference on Parallel,Distributed,and Network-Based Processing. Piscataway,NJ:IEEE Press,2016:771-776.
[5] Eghbal A,Yaghini P M,Bagherzadeh N,et al. Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip[J].IEEE Trans on Computers,2015,64(12):3591-3604.
[6]张大坤,宋国治,王莲莲,等.三维片上网络拓扑结构研究综述[J].计算机科学与探索,2015,9(2):129-164.(Zhang Dakun,Song Guozhi,Wang Lianlian,et al. Survey on topologies of three dimensional network-on-chip[J]. Journal of Frontiers of Computer Science&Technology,2015,9(2):129-164.)
[7] Feero B S,Pande P P. Networks-on-chip in a three-dimensional environment:a performance evaluation[J]. IEEE Trans on Computers,2009,58(1):32-45.
[8] Jiao Jiajia,Fu Yuzhuo,Liu Ting,et al. Performance analysis and optimization for homogenous multi-core system based on 3D torus network on chip[C]//Proc of NEWCAS Conference. Piscataway,NJ:IEEE Press,2010:313-316.
[9] Yin A W,Xu T C,Liljeberg P,et al. Explorations of honeycomb topologies for network-on-chip[C]//Proc of the 6th IFIP International Conference on Network and Parallel Computing. Piscataway,NJ:IEEE Press,2009:73-79.
[10]He Xu,You Zhiqiang,Kuang Jishun. Performance analysis of three dimensional hypercube network topology[D]. Beijing:University of China Science and Technology,2011.
[11]刘有耀,韩俊刚.片上网络拓扑结构与通信方法研究[D].西安:西安电子科技大学,2009.(Liu Youyao,Han Jungang. Research on network-on-chip topology and communication method[D]. Xi’an:Xidian University,2009.)
[12]张大坤,王光兴.基于群论的柏拉图立体着色方案三维模型构造[J].软件学报,2004,15(2):292-299.(Zhang Dakun,Wang Guangxing. Construction of three-dimensional model of Platonic solid coloring mode based on group theory[J]. Journal of Software,2004,15(2):292-299.)
[13]Hossain H,Ahmed M,Al-Nayeem A,et al. Gpnocsim:a general purpose simulator for network-on-chip[C]//Proc of International Conference on Information and Communication Technology. Piscataway,NJ:IEEE Press,2007:254-257.