交互式两阶段评估演化策略在容错系统中的应用
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摘要
随着电子技术的飞速发展,电子产品的微型化和智能化使其成为人们日常生活的重要组成部分,由此人们对系统的稳定性和可靠性提出了更高的要求,容错技术已成为当前研究热点。全文首先提出一种三模异构冗余容错系统架构平台,该平台利用演化机制有效构建成功个体池,从而确保系统中三个冗余模块出错时的实时修复能力。为了进一步提高成功个体池中演化个体生成效率,引入交互式两阶段评估演化策略,从演化个体适应值及个体间的异构度两方面评估优化对系统性能进行了改进。最终以三位乘法器为例进行实验,结果表明该演化策略在演化效率上明显高于传统1+λ演化策略,同时也确保了系统生成个体的多样性,增强了该平台的容错性能。
With the rapid development of digital electronic technology,electronic product with miniaturization and intelligence has become an important part of daily life. At the same time,people have made more requirements towards the stability and reliability of electronic product. Fault-tolerance technology has become the hot spot of research currently. The paper firstly puts forward the fault-tolerance architecture platform based on triple different-structure Modular Redundancy system,which effectively build a successful individual pool by evolution mechanism to ensure the real-time fault-tolerant of the system. And then,the interactive two-stage assessment evolution strategy is proposed,which improved the performance of the system by promoting evolution efficiency and heterogeneous degree of evolution individuals. Finally,the proposed scheme is tested with the evolution of a 3-bit multiplier. The results show that the interactive two-stage assessment evolution strategy has significantly higher efficiency than 1+λES,ensures the diversity of individuals in the successful individual pool,and enhances the fault-tolerant performance of the platform.
With the rapid development of digital electronic technology,electronic product with miniaturization and intelligence has become an important part of daily life. At the same time,people have made more requirements towards the stability and reliability of electronic product. Fault-tolerance technology has become the hot spot of research currently. The paper firstly puts forward the fault-tolerance architecture platform based on triple different-structure Modular Redundancy system,which effectively build a successful individual pool by evolution mechanism to ensure the real-time fault-tolerant of the system. And then,the interactive two-stage assessment evolution strategy is proposed,which improved the performance of the system by promoting evolution efficiency and heterogeneous degree of evolution individuals. Finally,the proposed scheme is tested with the evolution of a 3-bit multiplier. The results show that the interactive two-stage assessment evolution strategy has significantly higher efficiency than 1+λES,ensures the diversity of individuals in the successful individual pool,and enhances the fault-tolerant performance of the platform.
引文
[1]聂鑫.基于演化硬件的数字电路容错方法研究[D].武汉:武汉大学博士论文,2011.
[2]徐拾义.容错计算系统[M].武汉:武汉大学出版社,2010:6.
[3]X Yao,T Higuchi.Promises and Challenges of Evolvable Hardware[J].IEEE Transactions on Systems,Man,and Cybernetics-Part C:Applications and Reviews,1999,29(1):87-97.
[4]Garrison W Greenwood,Andtrew M Tyrrell.Introduction to Evolvable Hardware:A Practical Guide for Designing SelfAdaptive Systems[M].Wiley-IEEE Press,2006:10.
[5]Jianan Lou,Chuantao Li,Jianhua Yu,and Jie Chu.Design and Realization on Evolvable Circuit Self-Repair[C].Proceedings of the 2013 International Conference on Mechatronics and Automatic Control Systems(ICMS2013),pp.509-516.
[6]姚睿,王友仁,于盛林,陈则王.具有在线修复能力的强容错三模冗余系统设计与实验研究[J].电子学报,2010,38(1):177-183.
[7]Greenwood G,Tyrrell AM.Metamorphic systems:a new model for adaptive system design[C].Proc.2010 Congress on Evolutionary Computation,IEEE,pp.3261-3268.
[8]李康顺,梁久生,张文生,李元香.一种基于GEP的演化硬件复杂电路优化算法[J].计算机工程与应用,2008.44(18):83-86.
[9]J.F.Miller,P.Thomson.Cartesian genetic programming[C].Proc.3rd Eur.Conf.Genetic Programming,2000,vol.1802,pp.12-132.
[10]Mihai Oltean,Crina Grosan.Evolving Digital Circuits using Multi Expression Programming[C].NASA/Do D Conference on Evolution Hardware,2004.
[11]James Alfred Walker,Martin A Trefzer and Andy M Tyrrell.Designing Function Configuration Decoders for the PAn DA architecture using Multi-objective Cartesian Genetic Programming[J].Evolvable Systems(ICES),2013,4:19-21.
[12]Zdenek Vasicek.Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates[C].Euro GP 2015,LNCS 9025,pp.139-150.
[13]宋学君,崔艳莉,薛志坤,等.数字电路模块化进化算法[J].北京工业大学学报,2014,40(7):1048-1053.
[14]朱继祥.自适应演化硬件及其容错技术研究[D].武汉:武汉大学博士论文,2010.
[15]J.F.Miller,P.Thomson.Cartesian genetic programming[C].In Proc.3rd Eur.Conf.Genetic Programming(Euro GP 2000),vol.1802,Lecture Notes in Computer Science,pp.121-132.
[16]Martin A.Trefzer,Andy M.Tyrrell.Evolvable Hardware From Practice to Application[M].Berlin:Springer Berlin Heidelberg,2015.
[2]徐拾义.容错计算系统[M].武汉:武汉大学出版社,2010:6.
[3]X Yao,T Higuchi.Promises and Challenges of Evolvable Hardware[J].IEEE Transactions on Systems,Man,and Cybernetics-Part C:Applications and Reviews,1999,29(1):87-97.
[4]Garrison W Greenwood,Andtrew M Tyrrell.Introduction to Evolvable Hardware:A Practical Guide for Designing SelfAdaptive Systems[M].Wiley-IEEE Press,2006:10.
[5]Jianan Lou,Chuantao Li,Jianhua Yu,and Jie Chu.Design and Realization on Evolvable Circuit Self-Repair[C].Proceedings of the 2013 International Conference on Mechatronics and Automatic Control Systems(ICMS2013),pp.509-516.
[6]姚睿,王友仁,于盛林,陈则王.具有在线修复能力的强容错三模冗余系统设计与实验研究[J].电子学报,2010,38(1):177-183.
[7]Greenwood G,Tyrrell AM.Metamorphic systems:a new model for adaptive system design[C].Proc.2010 Congress on Evolutionary Computation,IEEE,pp.3261-3268.
[8]李康顺,梁久生,张文生,李元香.一种基于GEP的演化硬件复杂电路优化算法[J].计算机工程与应用,2008.44(18):83-86.
[9]J.F.Miller,P.Thomson.Cartesian genetic programming[C].Proc.3rd Eur.Conf.Genetic Programming,2000,vol.1802,pp.12-132.
[10]Mihai Oltean,Crina Grosan.Evolving Digital Circuits using Multi Expression Programming[C].NASA/Do D Conference on Evolution Hardware,2004.
[11]James Alfred Walker,Martin A Trefzer and Andy M Tyrrell.Designing Function Configuration Decoders for the PAn DA architecture using Multi-objective Cartesian Genetic Programming[J].Evolvable Systems(ICES),2013,4:19-21.
[12]Zdenek Vasicek.Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates[C].Euro GP 2015,LNCS 9025,pp.139-150.
[13]宋学君,崔艳莉,薛志坤,等.数字电路模块化进化算法[J].北京工业大学学报,2014,40(7):1048-1053.
[14]朱继祥.自适应演化硬件及其容错技术研究[D].武汉:武汉大学博士论文,2010.
[15]J.F.Miller,P.Thomson.Cartesian genetic programming[C].In Proc.3rd Eur.Conf.Genetic Programming(Euro GP 2000),vol.1802,Lecture Notes in Computer Science,pp.121-132.
[16]Martin A.Trefzer,Andy M.Tyrrell.Evolvable Hardware From Practice to Application[M].Berlin:Springer Berlin Heidelberg,2015.