面向MLC STT-RAM的寄存器分配策略优化研究
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摘要
多级自旋转移力矩磁性存储器(MLC STT-RAM)是一种新型的非易失性存储介质。不同于采用电荷方式来存储信息的SRAM,MLC STT-RAM利用自旋偏振电流通过磁隧道结(MTJ)改变自由层的磁层方向来存储信息,能够天然地避免电磁干扰。文章利用MLC STT-RAM的抗电磁辐射特性,探索在航天抗辐照环境下将其作为存储介质用于寄存器设计。在MLC STT-RAM中,每个存储单元有4种不同的阻抗状态,不同的阻抗状态之间的转换具有不同的能耗和延迟的代价。而传统的基于SRAM的寄存器分配技术并没有考虑不同的写状态转换的影响,其在没有考虑溢出优先级的情况下启发式地选择潜在溢出变量,因此该方法不适合用在MLC STT-RAM的寄存器分配中。针对该问题,提出了一种面向写状态转换的MLC STT-RAM寄存器分配的溢出优化策略。具体来说,首先,通过每个写状态转换频率的线性组合来构成溢出代价模型。然后,根据溢出代价模型针对性地选择溢出变量,选择代价低的变量保存在寄存器中,而代价高的变量倾向于被溢出,从而便实现了面向MLC STT-RAM的寄存器分配策略的优化设计。
Multi-level cell spin-transfer torque random access memory(MLC STT-RAM)is a promising nonvolatile memory technology.Unlike the SRAM that uses a charge mode to store information,MLC STT-RAM uses the spin polarization current to change the magnetic layer direction of the free layer through the magnetic tunneling junction(MTJ)to store information,so it can naturally avoid electromagnetic interference.This paper used the anti-electromagnetic radiation characteristics of MLC STT-RAM,and explored it as a register for its natural immunity to electromagnetic radiation in rad-hard space environment.MLC STT-RAM exhibits unbalanced write-state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped.This feature leads to nonuniform costs of write-states in terms of latency and energy.However,current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write-state transition costs.As a result,those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM.Aiming to address this limitation,this paper proposed a state-transition aware spilling cost minimization(SSCM)policy to save power when MLC STT-RAM is employed in register design.Specifically,the spilling cost model is first constructed according to the linear combination of different state transition frequencies.Directed by the proposed cost model,the compiler picks up spilling candidates with the highest cost to achieve lower power and higher performance.
Multi-level cell spin-transfer torque random access memory(MLC STT-RAM)is a promising nonvolatile memory technology.Unlike the SRAM that uses a charge mode to store information,MLC STT-RAM uses the spin polarization current to change the magnetic layer direction of the free layer through the magnetic tunneling junction(MTJ)to store information,so it can naturally avoid electromagnetic interference.This paper used the anti-electromagnetic radiation characteristics of MLC STT-RAM,and explored it as a register for its natural immunity to electromagnetic radiation in rad-hard space environment.MLC STT-RAM exhibits unbalanced write-state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped.This feature leads to nonuniform costs of write-states in terms of latency and energy.However,current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write-state transition costs.As a result,those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM.Aiming to address this limitation,this paper proposed a state-transition aware spilling cost minimization(SSCM)policy to save power when MLC STT-RAM is employed in register design.Specifically,the spilling cost model is first constructed according to the linear combination of different state transition frequencies.Directed by the proposed cost model,the compiler picks up spilling candidates with the highest cost to achieve lower power and higher performance.
引文
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[2]姚君.STT-RAM缓存优化策略的研究[D].杭州:浙江工业大学,2014.
[3]CHABI D,ZHAO W S,JACQUES-OLIVIER K,et al.Design and analysis of radiation hardened sensing circuits for spin transfer torque magnetic memory and logic[J].IEEE Transactions on Nuclear Science,2014,61(6):3258-3264.
[4]HUGHES H,BUSSMANN K,MCMARR P J.et al.Radiation studies of spin-transfer torque materials and devices[J].IEEE Transactions on Nuclear Science,2012,59(6):3027-3033.
[5]BISHNOI R,EBRAHIMI M,OBORIL F,et al.Improving write performance for STT-MRAM[J].IEEE Transactions on Magnetics,2016,52(8):1-11.
[6]赵巍胜,王昭昊,彭守仲,等.STT-MRAM存储器的研究进展[J].中国科学:物理学力学天文学,2016,46(10):107306.
[7]董伟.基于NVM的写操作优化策略研究与设计[D].济南:山东大学,2016.
[8]李清安.面向非易失性片上存储的编译技术研究[D].武汉:武汉大学,2013.
[9]CHEN Y R,WANG X B,ZHU W Z,et al.Access scheme of multi-level cell spin-transfer torque random access memory and its optimization[C]∥Midwest Symposium on Circuits and Systems.2010:1109-1112.
[10]何炎祥,沈凡凡,张军,等.新型非易失性存储器架构的缓存优化方法综述[J].计算机研究与发展,2015,52(6):1225-1241.
[11]CHAITIN,AUSLANDER,CHANDRA,et al.P.W.:Register allocation via graph coloring[J].Journal of Computer Languages,1981,238(16):265-266.
[12]COOPER K,DASGUPTA A,et al.Tailoring graph-coloring register allocation for runtime compilation[C]∥Code Generation and Optimization.2006:39-49.
[13]张军超.相连多寄存器组体系结构上的寄存器分配技术[D].中国科学院研究生院(计算技术研究所),2005.
[14]邓宇.基于图着色的存储层次优化技术研究[D].长沙:国防科学技术大学,2007.
[15]薛丽萍.基于龙芯I的全局寄存器分配研究[D].中国科学院研究生院(计算技术研究所),2004.
[16]FALK H.WCET-aware register allocation based on graph coloring[C]∥Design Automation Conference.2009:726-731.
[17]LOU X H,GAO Z,DIMITORV,et al.Demonstration of multilevel cell spin transfer switching in mgo magnetic tunnel junctions[J].Applied Physics Letters,2008,93(24):242-502.
[18]ZHAO M Y,XUE Y,YANG C M,et al.Minimizing MLC PCM write energy for free through profiling-based state remapping[C]∥Asia and South Pacific Design Automation Conference.2015:502-507.
[19]ZHAO M Y,XUE Y,HU J T,et al.State asymmetry driven state remapping in phase change memory[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2016,36(1):27-40.
[20]LIU X X,MAO M J,BI X Y,et al.An efficient stt-ram-based register file in gpu architectures[C]∥Asia and South Pacific Design Automation Conference.2015:490-495.
[21]LATTNER C,ADVE V.LLVM:A compilation framework for lifelong program analysis&transformation[C]∥Code Generation and Optimization.2004:75-86.
[22]LUO H Z,HU J T,SHI L,et al.Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM[C]∥Design Automation Conference.2016:1-6.