一种CMOS工艺的ATC芯片的设计
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摘要
基于CSMC 2P2M0.6μm CMOS工艺设计了一种全数字的模拟-时间转换芯片(Analog to Time Conversion:ATC).电路由核心电路单元、电平转换电路单元、ESD保护电路单元和输出缓冲器电路单元组成.整体电路采用Hspice和CSMC 2P2M的CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M CMOS工艺完成版图设计,版图面积为1mm~2,并参与MPW(多项目晶圆)计划流片,流片测试结果表明,芯片满足设计目标,并可以IP核的形式应用于各种数字集成电路的设计中.
A analog to time conversion digital chip is designed based on CSMC 2 P2 M0.6μm CMOS process.This circuit includes core circuit cell,Level Translator cell,ESD(Electro Static Discharge)protection cell and Output buffer cell.The circuit is simulated using Hspice and the process of the CSMC 2 P2 MCMOS(06 mixddct02 v24),the layout is based on CSMC2 P2 M CMOS and is used in a Multi-functional Digital Chip,The chip are a is 1 mm×1 mm.The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals.
A analog to time conversion digital chip is designed based on CSMC 2 P2 M0.6μm CMOS process.This circuit includes core circuit cell,Level Translator cell,ESD(Electro Static Discharge)protection cell and Output buffer cell.The circuit is simulated using Hspice and the process of the CSMC 2 P2 MCMOS(06 mixddct02 v24),the layout is based on CSMC2 P2 M CMOS and is used in a Multi-functional Digital Chip,The chip are a is 1 mm×1 mm.The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals.
引文
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[2]Toral S L,Quero J M,Ortega J G,et al.Stochastic A/D sigma-delta converter on FPGA[J].Midwest Symposium on Circuits and Systems,1999,1:35-38.
[3]Watanabe,Takamoto,Mizuno,et al.An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering[J].IEEE Journal of SolidState Circuits,2013,38(1):120-125.
[4]劳文华.IC测试系统中时间参数测量单元的研究[D].成都:电子科技大学,2014.
[5]哈继欣,高玉竹.用于多电压域设计的双向全摆幅电平转换器[J].上海师范大学学报(自然科学版),2012,41(5):466-469.
[6]弗兰克(MAYEDI BOUSSOUKOU Roland Franck).基于0.18μm CMOS工艺8位FLASH模数转换器的设计[D].哈尔滨:黑龙江大学,2014.
[7]周子昂,吴定允,徐坤,等.一种基于CMOS工艺的电平转换芯片[J].电子与封装,2011,95(03):22-24.
[8]Okushima Mototsugu,Noguchim Ko,Sawahata Koichi,et al.ESD protection Scheme using CMOS Compatible Vertical Bipolar Transistor for 130nm CMOS Generation[J].IEEE IEDM Tech Dig,2000:127-129.
[9]李静.TDI CMOS图像传感器列级ADC的研究与设计[D].天津:天津大学,2013.
[10]Fan Hang,Jiang Lingli,Zhang Bo.A novel ESD protection structure for output pads[J].Chinese Journal of Semiconductors,2013,11:95-98.
[11]杨兵,罗静,于宗光.深亚微米CMOS电路多电源全芯片ESD技术研究[J].电子器件,2012,35(3):258-262.
[12]陈子晏,马和良,陈磊,等.高性能多模可编程CMOS输出缓冲器的研究实现[J].电子器件,2008,31(5):1483-1486.
[13]易敬军,沈绪榜.双等比CMOS缓冲器的设计[J].微电子学与计算机,2003,20(1):62-66.
[14]黄春行,朱晓华.CMOS输出缓冲器瞬态行为的SPICE建模[J].南京理工大学学报(自然科学版),2005,29(1):43-45.