脉冲神经网络硬件系统性能监测平台
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摘要
随着脉冲神经网络规模不断增大、功能越来越复杂,如何快速地验证神经网络硬件系统结构各部分的功能,并准确地评估其性能成为设计者面临的严峻挑战。本文设计了一款可视化性能监测平台,用于脉冲神经网络硬件系统的功能验证和性能监测。以Xilinx Zynq-7000器件为例,测试结果表明该监测平台具有轻量化设计、良好的人机交互界面和通用性等优势,能够提高脉冲神经网络硬件系统的功能验证和性能评估效率,为其硬件系统设计提供了较好的辅助功能验证与性能分析手段。
With the increasing size of the spike neural network with very complicated functions,how to quickly verify the functions of the hardware system structure of the neural network,and accurately assess its performance has become a serious challenge for designers.A visualization performance monitoring platform is designed in this paper,which is used as functional verification and performance monitoring for the hardware SNNs.The monitoring platform takes the Xilinx Zynq-7000 device as an example and has the advantages of lightweight design,good human-computer interaction interface and versatility,and can improve the efficiency of system function verification and performance evaluation of SNN hardware structure.It provides auxiliary functional verification and performance analysis for the design of SNN hardware systems.
With the increasing size of the spike neural network with very complicated functions,how to quickly verify the functions of the hardware system structure of the neural network,and accurately assess its performance has become a serious challenge for designers.A visualization performance monitoring platform is designed in this paper,which is used as functional verification and performance monitoring for the hardware SNNs.The monitoring platform takes the Xilinx Zynq-7000 device as an example and has the advantages of lightweight design,good human-computer interaction interface and versatility,and can improve the efficiency of system function verification and performance evaluation of SNN hardware structure.It provides auxiliary functional verification and performance analysis for the design of SNN hardware systems.
引文
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[3]LOTLIKAR S,PAI V,GRATZ P V.AcENoCs:a configurable HW/SW platform for FPGA accelerated NoC emulation[C]//Proceedings of 24th International Conference on VLSI Design.Chennai,India:IEEE Press,2011:147-152.DOI:10.1109/VLSID.2011.46.
[4]JIANG N,MICHELOGIANNAKIS G,BECHER D,et al.Booksim 2.0User’s Guide[R].State of California:Standford University,2010.
[5]LIU Junxiu,HARKIN J,LI Yuhua,et al.Low cost fault-tolerant routing algorithm for networks-on-chip[J].Microprocessors and Microsystems,2015,39(6):358-372.DOI:10.1016/j.micpro.2015.06.002.
[6]WAN Lei,LIU Junxiu,HARKIN J,et al.Layered tile architecture for efficient hardware spiking neural networks[J].Microprocessors and Microsystems,2017,53(6):21-32.DOI:10.1016/j.micpro.2017.07.005
[7]CARRILLO S,HARKIN J,MCDAID L,et al.Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive Network-on-Chiprouters[J].Neural Networks,2012,33(9):42-57.DOI:10.1016/j.neunet.2012.04.004.
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