摘要
为了改进传统CAN(控制器局域网络)总线控制器设计方式,减少CAN总线通信系统的外围芯片数量,降低产品功耗,基于FPGA(现场可编程门阵列)嵌入式片上系统可编程技术对CAN总线控制器进行IP核(知识产权核)设计,并进行了优化升级,最后利用软件逻辑分析仪进行通信测试,将CAN控制器封装成IP核,证明了该CAN控制器IP核设计合理、时序正确,具有良好的工作性能。
In order to improve the traditional CAN(controller local area network)bus controller design approach,and reduce the number of peripheral chips of the CAN bus communication system and the power consumption of the product,the CAN bus controller of IP core nuclear is designed based on FPGA(field programmable gate array)technology,and the IP core is optimized.Finally the CAN controller and encapsulate IP core is embedded in the FPGA chip.The simulation test results show that the CAN controller IP core design is reasonable,the scheme is feasible,the timing is right and has good working performance.
引文
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