时钟频率校正关键技术研究
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摘要
设计了一种全数字时钟频率校正电路,其子电路结构包括相位检测器、低通滤波器和数控振荡器.详细说明了频率校正算法.仿真结果表明,该时钟频率校正电路具有精度高、可移植性好、抗干扰能力强的特点.
An all-digital clock frequency calibration system was designed. Sub circuit units including phase detector, low-pass filter and digital controlled oscillator were introduced, as well as the algorithm of frequency calibration. Simulation results show this clock frequency calibration system has a high performance of accuracy, portability and anti-interference ability.
An all-digital clock frequency calibration system was designed. Sub circuit units including phase detector, low-pass filter and digital controlled oscillator were introduced, as well as the algorithm of frequency calibration. Simulation results show this clock frequency calibration system has a high performance of accuracy, portability and anti-interference ability.
引文
1 Abbasizadeh H, Rikan B S, Lee K Y. A fully on-chip 25 MHz PVT-compensation CMOS relaxation oscillator[C/OL]//2015 IFIP/IEEE International Conference on Very Large Scale Integration, Daejeon, South Korea,Oct 5-7, 2015.[2017-03-15]. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7314423.
2 Wang Y, Chai K T C, Mu X, et al. A 1.5±0.39 ppm/℃temperature-compensated LC oscillator using constant-biased varactors[J]. IEEE Microwave&Wireless Components Letters, 2015, 25(2):130-132.
3 刘小峰,刘铛,李宇根,等.应用于超宽带收发机的多相时钟生成器的设计[J].微电子学与计算机, 2016, 33(11):87-90.
4 Park P, Park J, Park H, et al. An all-digital clock generator using a fractionally injection-locked oscillator in65 nm CMOS[C/OL]//2012 IEEE International Solid-state Circuits Conference, San Francisco, CA, USA, Feb19-23, 2012.[2017-03-15]. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7314423.
5 Huang Qiang, Fan Tao, Dai Xiangming, et al. A low-power DCO using inverter interlaced cascaded delay cell[J]. Journal of Semiconductors, 2014, 35(11):119-124.
6 谢谦,梁国辉,刘俊杰,等. 90 nm CMOS全数字锁相环设计与实现[J].微电子学, 2012, 42(1):1-4.
7 邓军勇,蒋林,曾泽沧.高速CMOS时钟数据恢复电路的设计与仿真[J].微电子学与计算机, 2014(11):56-63.
8 Chen P L, Chung C C, Lee C Y. A portable digitally controlled oscillator using novel varactors[J]. IEEE Transactions on Circuits&Systems II:Express Briefs, 2005, 52(5):233-237.
2 Wang Y, Chai K T C, Mu X, et al. A 1.5±0.39 ppm/℃temperature-compensated LC oscillator using constant-biased varactors[J]. IEEE Microwave&Wireless Components Letters, 2015, 25(2):130-132.
3 刘小峰,刘铛,李宇根,等.应用于超宽带收发机的多相时钟生成器的设计[J].微电子学与计算机, 2016, 33(11):87-90.
4 Park P, Park J, Park H, et al. An all-digital clock generator using a fractionally injection-locked oscillator in65 nm CMOS[C/OL]//2012 IEEE International Solid-state Circuits Conference, San Francisco, CA, USA, Feb19-23, 2012.[2017-03-15]. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7314423.
5 Huang Qiang, Fan Tao, Dai Xiangming, et al. A low-power DCO using inverter interlaced cascaded delay cell[J]. Journal of Semiconductors, 2014, 35(11):119-124.
6 谢谦,梁国辉,刘俊杰,等. 90 nm CMOS全数字锁相环设计与实现[J].微电子学, 2012, 42(1):1-4.
7 邓军勇,蒋林,曾泽沧.高速CMOS时钟数据恢复电路的设计与仿真[J].微电子学与计算机, 2014(11):56-63.
8 Chen P L, Chung C C, Lee C Y. A portable digitally controlled oscillator using novel varactors[J]. IEEE Transactions on Circuits&Systems II:Express Briefs, 2005, 52(5):233-237.