一种基于JTAG接口的SIP测试调试系统设计技术
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  • 英文篇名:Design Technique of a SIP Test and Debugging System Based on JTAG Interface
  • 作者:杨亮 ; 于宗光 ; 魏敬和
  • 英文作者:Yang Liang;Yu Zongguang;Wei Jinghe;The 58th Research Institute,CETC;
  • 关键词:联合测试行动组(JTAG) ; 系统级封装(SIP) ; 无损测试 ; 片上系统(SOC) ; LabView软件
  • 英文关键词:joint test action group(JTAG);;system in package(SIP);;nondestructive test;;system on chip(SOC);;Lab View software
  • 中文刊名:BDTJ
  • 英文刊名:Semiconductor Technology
  • 机构:中国电子科技集团公司第五十八研究所;
  • 出版日期:2018-04-03
  • 出版单位:半导体技术
  • 年:2018
  • 期:v.43;No.356
  • 基金:国家自然科学基金资助项目(61704161)
  • 语种:中文;
  • 页:BDTJ201804014
  • 页数:5
  • CN:04
  • ISSN:13-1109/TN
  • 分类号:81-85
摘要
随着系统级封装(SIP)的内部器件数量和规模的不断增长,SIP内部器件的可测性、可调试性以及SIP后的可靠性问题变得越来越突出。当SIP器件在使用过程中出现问题,进行无损测试定位的难度也越来越大。为此,针对一款集成了片上系统(SOC)、一片四通道模拟数字转换器(ADC)、两片两通道数字模拟转换器(DAC)和多个无源器件的SIP系统,开发了基于联合测试行动组(JTAG)接口的能复用中央处理器(CPU)调试软件的SIP测试调试技术。该技术通过复用SOC自有的JTAG引脚,实现对SIP内各个器件的测试。编写了基于Lab View软件的图形化测试程序,提高了测试效率。测试结果表明,设计的SIP测试调试系统能够完好地复用CPU的调试软件并完成测试工作,满足设计要求和测试调试需求,为后续集成更多器件的SIP测试奠定了良好的技术基础。
        With the increasing number and scale of internal devices in system in package( SIP),the problems of testability and debugging of internal devices in SIP and reliability after SIP are becoming more and more prominent. When the SIP device comes up with problems in application process,it is more and more difficult to take nondestructive test and positioning. Thus,for a SIP system integrated with a system on chip( SOC),a four-channel analog-to-digital converter( ADC),two two-channel digital-toanalog converters( DACs) and multiple passive devices,a SIP test and debugging technique was developed based on joint test action group( JTAG) interface,which can multiplex the central processing unit( CPU) debugging software. The technology multiplexed the JTAG pins of SOC to achieve the test of each device within SIP. A graphical test program based on Lab View software was written to improve the test efficiency. The test results show that the designed SIP test and debugging system can perfectly reuse the CPU debugging software and complete the testing work to meet the design requirements and testing and debugging requirements,laying a good technical foundation for later SIP testing for integrating more devices.
引文
[1]崔明礼.基于JTAG标准的SOC调试研究与实现[D].哈尔滨:哈尔滨工程大学,2008.
    [2]LU J Q.3-D hyperintegration and packaging technologies for micro-nano systems[J].Proceedings of the IEEE,2009,97(1):18-30.
    [3]过方舟,徐锐敏.系统级封装关键技术研究进展[J].微波学报,2014,30(S1):588-593.GUO F Z,XU R M.Research of key technology in system in package[J].Journal of Microwaves,2014,30(S1):588-593(in Chinese).
    [4]WANG R,CHAKRABARTY K,BHAWMIK S.Built-in self-test for interposer-based 2.5D ICs[C]∥Proceedings of the 32ndInternational Conference on Computer Design.Seoul,South Korea,2014:181-188.
    [5]CHOU C W,LI J F,YU Y C,et al.Hierarchical test integration methodology for 3-D ICs[J].IEEE Design&Test,2015,32(4):59-70.
    [6]de JONG F G M,BIEWENGA A S.Testable integrated circuit,system in package and test instruction set:US7948243B2[P].2011-05-24.
    [7]STANLEY M E,VACCARO J S.Methods and apparatus for testing multiple-IC devices:US8756467B2[P].2014-06-17.
    [8]杨欣然,吴琼之,范秋香.多通道实时阵列信号处理系统的设计[J].电子设计工程,2015,23(12):176-179.YANG X R,WU Q Z,FAN Q X.Design of multichannel real-time array signal processing system[J].Electronic Design Engineering,2015,23(12):176-179(in Chinese).
    [9]孙毅刚,何进.基于Lab VIEW的高精度多通道温度测量系统[J].仪表技术与传感器,2017(1):96-100.SUN Y G,HE J.Multi-channel temperature measurement system of high-precision based on Lab VIEW[J].Instrument Technique and Sensor,2017(1):96-100(in Chinese).

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