9～11GHz数字控制LC振荡器
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摘要
采用TSMC65nm CMOS工艺设计了用于全数字频率综合器、频率覆盖范围8.95～11.02GHz的数字控制LC振荡器。为了减小相位噪声,本设计采用了带有尾电感的互补型LC振荡器结构;振荡器的可编程电容阵列被分成3组,以此来配合数字频率综合器的3个频率锁定过程。在电源电压为1V的情况下,振荡器的功耗为3.53mW。测试结果显示,该数字控制LC振荡器实现了40kHz的频率精度,当输出频率为9.38GHz时,在1MHz频偏处,相位噪声为-111.02dBc/Hz。
A digital-controlled LC oscillator is implemented in TSMC 65 nm CMOS process,which is used in all digital frequency synthesizer with an output frequency range from 8.95 GHz to 11.02 GHz.In order to reduce the phase noise,the complementary structure with tail inductors is used.The capacitor banks are divided into three parts in order to coordinate with the three steps of frequency locking process of the synthesizer.Under a supply of 1 V,the power consumption is 3.53 mW.According to the measurement results,a frequency resolution of 40 kHz is realized and the phase noise at 9.38 GHz is-111.02 dBc/Hz at 1 MHz offset.
A digital-controlled LC oscillator is implemented in TSMC 65 nm CMOS process,which is used in all digital frequency synthesizer with an output frequency range from 8.95 GHz to 11.02 GHz.In order to reduce the phase noise,the complementary structure with tail inductors is used.The capacitor banks are divided into three parts in order to coordinate with the three steps of frequency locking process of the synthesizer.Under a supply of 1 V,the power consumption is 3.53 mW.According to the measurement results,a frequency resolution of 40 kHz is realized and the phase noise at 9.38 GHz is-111.02 dBc/Hz at 1 MHz offset.
引文
[1]Robert Bogdan Staszewski,Poras T Balsara.All-Digital Frequency Synthesizer in Deep-submicronCMOS[M].Hoboken,NY:John Wiley&Sons,2006.
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[3]Ali Hajimiri,Thmoas H Lee.A general theory ofphase noise in electrical oscillators[J].IEEE Journalof Solid-statcircuits.1998,33(2):179-194.
[4]Hegazi E,Sjoland H,Abidi A A.A filteringtechnique to lower LC oscillator phase noise[J].IEEEJournal of Solid-Statcircuits,2001,36(12):1921-1930.
[5]Han J H,Cho S H.Digitally controlled oscillator withhigh frequency resolution using novel varactor bank[J].Electronics Letters,2008,44(25):1450-1452.
[6]Yoo Sang-Sun,Choi Yong-Chang,Song Hong-Joo,et al.A 5.8 GHz high-frequency resolution digitallycontrolled oscillator using the difference betweenInversion and accumulation mode capacitance of pMOSvaractors[J].IEEE Transactions on MicrowaveTheory and Techniques,2011,59(2):375-382.
[7]Luca Fanori,Antonio Liscidini,Rinaldo Castello.3.3GHz DCO with a frequency resolution of 150 Hz forall-digital PLL[C].ISSCC,2010:48-50.
[8]Antonio Liscidini,Luca Fanori,Pietro Andreani,etal.A 36 mW/9 mW power-scalable DCO in 55 nmCMOS for GSM/WCDMA frequency synthesizers[C].ISSCC,2012:348-350.
[2]Ali Hajimiri,Thomas H Lee.Design issues in CMOSdifferential LC oscillators[J].IEEE Journal of Solid-stat Circuits,1999,34(5):717-724.
[3]Ali Hajimiri,Thmoas H Lee.A general theory ofphase noise in electrical oscillators[J].IEEE Journalof Solid-statcircuits.1998,33(2):179-194.
[4]Hegazi E,Sjoland H,Abidi A A.A filteringtechnique to lower LC oscillator phase noise[J].IEEEJournal of Solid-Statcircuits,2001,36(12):1921-1930.
[5]Han J H,Cho S H.Digitally controlled oscillator withhigh frequency resolution using novel varactor bank[J].Electronics Letters,2008,44(25):1450-1452.
[6]Yoo Sang-Sun,Choi Yong-Chang,Song Hong-Joo,et al.A 5.8 GHz high-frequency resolution digitallycontrolled oscillator using the difference betweenInversion and accumulation mode capacitance of pMOSvaractors[J].IEEE Transactions on MicrowaveTheory and Techniques,2011,59(2):375-382.
[7]Luca Fanori,Antonio Liscidini,Rinaldo Castello.3.3GHz DCO with a frequency resolution of 150 Hz forall-digital PLL[C].ISSCC,2010:48-50.
[8]Antonio Liscidini,Luca Fanori,Pietro Andreani,etal.A 36 mW/9 mW power-scalable DCO in 55 nmCMOS for GSM/WCDMA frequency synthesizers[C].ISSCC,2012:348-350.