摘要
针对IEEE 1588v2主时钟到从时钟的时延和从时钟到主时钟的时延不相等的问题,构建了一种三层BP神经网络模型,将基于时间戳的主从时钟偏差计算结果输入该网络模型,对时间偏差进行补偿。实验结果表明:该方法能够将非对称链路的时钟同步精度由100μs提升至50μs,同时消除过大的抖动,从而更好地校正传输时延。
Aiming at the problem that the IEEE 1588 v2 master clock to slave clock delay and the slave clock to master clock delay are not equal, a three-layer BP neural network model is constructed, the calculation results of master-slave clock deviation based on timestamp are input into this network model to compensate the time deviation. The experiment results demonstrate that this model can improve the clock synchronization accuracy of asymmetric links from 100 μs to 50 μs, while eliminating excessive jitter, thus better correcting the transmission delay.
引文
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