基于新型时间放大器流水线时间数字转换器
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摘要
针对传统时间数字转换器(TDC)中普遍存在的转换速度与转换精确度相互制约问题,提出一种适用于流水线型TDC结构的新型边沿对准时间放大器。这种时间放大器采用三级门控延时链与边沿合成器的级联结构,可实现增益为4的整数倍时间放大。在0.35μm标准CMOS工艺下完成整体流水线型TDC的设计,仿真结果显示,输入动态范围为6.11 ns,时间分辨力为13.1 ps,转换速率为50 MSamples/s。相比于传统基于脉冲序列时间放大器的TDC,转换速率提高19.5%,精确度提高33.7%。
A novel Edge Align-Time Amplifier(EA-TA) is proposed aiming at improving the trade-off between conversion rate and precision in traditional Time-to-Digital Converter(TDC). This time amplifier in pipeline TDC consists of 3 cascaded gated delay lines and edge combiner to achieve an integral gain of 4. The pipelined TDC is implemented in standard 0.35 μm CMOS process. Full simulation results show that the TDC can achieve 13.1 ps of resolution at 50 MSamples/s while the dynamic input range is 6.11 ns. Compared to other time amplifier such as Pulse Train-Time Amplifier(PT-TA), the proposed edge-align time amplifier can get 19.5% and 33.7% higher in conversion rate and precision respectively.
A novel Edge Align-Time Amplifier(EA-TA) is proposed aiming at improving the trade-off between conversion rate and precision in traditional Time-to-Digital Converter(TDC). This time amplifier in pipeline TDC consists of 3 cascaded gated delay lines and edge combiner to achieve an integral gain of 4. The pipelined TDC is implemented in standard 0.35 μm CMOS process. Full simulation results show that the TDC can achieve 13.1 ps of resolution at 50 MSamples/s while the dynamic input range is 6.11 ns. Compared to other time amplifier such as Pulse Train-Time Amplifier(PT-TA), the proposed edge-align time amplifier can get 19.5% and 33.7% higher in conversion rate and precision respectively.
引文
[1]CHENG Zeng,DEEN M J,PENG Hao.A low-power gateable Vernier ring oscillator time-to-digital converter for biomedical imaging applications[J].IEEE Transactions on Biomedical Circuits and Systems,2016,10(2):445-454.
[2]SEO Y H,LEE S K,SIM J Y.A 1-GHz digital PLL with a 3-ps resolution floating-point-number TDC in a 0.18-μm CMOS[J].IEEE Transactions on Circuits and System-II Express Briefs,2011,58(2):70-74.
[3]DUDEK P,SZCZEPANSKI S,HATFIELD J V.A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line[J].IEEE Journal of Solid-State Circuits,2000,35(2):240-247.
[4]LISCIDINI A,VERCESI L,CASTELLO R.Time to digital converter based on a 2-dimensions Vernier architecture[C]//IEEE Custom Integrated Circuits Conference.Rome,Italy:IEEE,2009:45-48.
[5]SEO Y H,KIM J S,PARK H J,et al.A 1.25 ps resolution 8b cyclic TDC in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2012,47(3):736-743.
[6]PEKKA K,JUHA K.A wide range 4.2 ps(rms)precision CMOS TDC with cyclic interpolators based on switched-frequency ring oscillators[J].IEEE Transactions on Circuits and System-I Regular Papers,2015,62(12):2795-2805.
[7]KIM K S,YU W S,CHO S H.A 9 bit 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register[J].IEEE Journal of Solid-State Circuits,2014,49(4):1007-1016.
[8]LEE M,ABIDI A A.A 9 b,1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifier a time residue[J].IEEE Journal of Solid-State Circuits,2008,43(4):769-777.
[9]LI S,CHRISTOPHER D S.Compact algorithmic time-to-digital converter[J].Electronics Letters,2015,51(3):213-215.
[10]XING N,SHIN W K,JEONG D K,et al.High-resolution time-to-digital converter utilizing fractional difference conversion scheme[J].Electronics Letters,2010,46(6):398-400.
[11]MARKOVIC B,TISA S,VILLA F,et al.A high-linearity 17 ps precision time-to-digital converter based on a single-stage Vernier delay loop fine interpolation[J].IEEE Transactions on Circuits and System-I Regular Papers,2013,60(3):557-569.
[12]叶超,冯莉,欧阳艳晶.基于FPGA的精密时间间隔测量仪设计[J].太赫兹科学与电子信息学报,2009,7(2):159-163.(YE Chao,FENG Li,OUYANG Yanjing.A design for the precise time-interval measuring instrument based on FPGA[J].Journal of Terahertz Science and Electronic Information Technology,2009,7(2):159-163.)
[2]SEO Y H,LEE S K,SIM J Y.A 1-GHz digital PLL with a 3-ps resolution floating-point-number TDC in a 0.18-μm CMOS[J].IEEE Transactions on Circuits and System-II Express Briefs,2011,58(2):70-74.
[3]DUDEK P,SZCZEPANSKI S,HATFIELD J V.A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line[J].IEEE Journal of Solid-State Circuits,2000,35(2):240-247.
[4]LISCIDINI A,VERCESI L,CASTELLO R.Time to digital converter based on a 2-dimensions Vernier architecture[C]//IEEE Custom Integrated Circuits Conference.Rome,Italy:IEEE,2009:45-48.
[5]SEO Y H,KIM J S,PARK H J,et al.A 1.25 ps resolution 8b cyclic TDC in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2012,47(3):736-743.
[6]PEKKA K,JUHA K.A wide range 4.2 ps(rms)precision CMOS TDC with cyclic interpolators based on switched-frequency ring oscillators[J].IEEE Transactions on Circuits and System-I Regular Papers,2015,62(12):2795-2805.
[7]KIM K S,YU W S,CHO S H.A 9 bit 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register[J].IEEE Journal of Solid-State Circuits,2014,49(4):1007-1016.
[8]LEE M,ABIDI A A.A 9 b,1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifier a time residue[J].IEEE Journal of Solid-State Circuits,2008,43(4):769-777.
[9]LI S,CHRISTOPHER D S.Compact algorithmic time-to-digital converter[J].Electronics Letters,2015,51(3):213-215.
[10]XING N,SHIN W K,JEONG D K,et al.High-resolution time-to-digital converter utilizing fractional difference conversion scheme[J].Electronics Letters,2010,46(6):398-400.
[11]MARKOVIC B,TISA S,VILLA F,et al.A high-linearity 17 ps precision time-to-digital converter based on a single-stage Vernier delay loop fine interpolation[J].IEEE Transactions on Circuits and System-I Regular Papers,2013,60(3):557-569.
[12]叶超,冯莉,欧阳艳晶.基于FPGA的精密时间间隔测量仪设计[J].太赫兹科学与电子信息学报,2009,7(2):159-163.(YE Chao,FENG Li,OUYANG Yanjing.A design for the precise time-interval measuring instrument based on FPGA[J].Journal of Terahertz Science and Electronic Information Technology,2009,7(2):159-163.)