摘要
提出以一个可获得高的分辨率和宽的信号带宽的二阶ΔΣ时间数字转换器(TDC),TDC基于门控环形振荡器型TDC并结合时间差加法器构成的时间累加器实现了二阶量化噪声整形。采用SMIC 28nm工艺设计,Spectre仿真结果表明,在1 M带宽内噪声底约为-82 d Bps~2/Hz,等效到50 Ms/s奈奎斯特率型TDC的分辨率约为2 ps,功耗取决于输入时间间隔,在测量间隔1ns时功耗约为1.19 mW。受到结构限制,这种类型时间数字转换器输入范围较小。
A second order ΔΣ Time-to-Digital Converter( TDC) is proposed to achieve high resolution and wide signal bandwidth.The proposed TDC based on gated-ring oscillator( GRO)-based TDC achieves second order quantization noise shaping with a time accumulator using time difference adders. Implemented in SMIC 28 nm CMOS process. Spectre simulation results show the noise floor of the TDC within 1 M bandwidth is about-82 d Bps~2/Hz which corresponds to a 50 Ms/s Nyquist-rate TDC and with 2 ps steps. The TDC power consumption depends on the time difference between input edges, typically about 1. 19 mW for 1 ns interval measurement. Limited by the structure, the input range of this type of TDC is small.
引文
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