QFP封装互连结构电气特性建模与退化分析
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摘要
互连结构是电子器件与印刷电路板之间机械固定及电气互联的关键部位.针对当前互连结构退化过程监测困难与表征信号难以提取问题,首先,通过分析QFP封装互连结构的失效模式及机理,建立其退化电气模型.在此基础上,搭建实时监测电路,选取外接电容的充电时间为表征信号,并建立退化电气模型参数与充电时间的关系.然后,利用Multisim软件和开发板模拟并验证等效电气模型参数与充电时间的关联关系.最后,利用小系统试验板进行随机振动试验,研究互连结构退化过程.通过分析充电时间响应,并结合互连结构电镜图发现,充电时间能够较好地表征互连结构的失效过程及失效模式.
The interconnection structure is a key part between the electrical device and the printed circuit board as the mechanical fixing and electrical interconnection. Aiming at the difficulties in real-time monitoring and extracting characterization signals for the health status of interconnects,firstly,a degenerate electrical model was established in this paper,by analyzing the failure modes and mechanisms of the QFP interconnect structure. Then, according to the degraded electrical model of the interconnect structure,a real-time monitoring circuit was built,with the charging time of the external capacitor selected as the characterization signal, and the relationship between the electrical parameters of the degradation model and the charging time was established. Afterwards, the Multisim and the development board had been used to simulate and verify the relationship between the equivalent electrical model parameters and the charging time in the degradation process of the interconnect structure. Finally, in order to analyze the degradation process of interconnects,a small system test board was used for random vibration test. From the results,combined with the electron microscope image of the interconnect structure, it was found that the charge time can characterize the failure process and failure mode of the interconnect structure well.
The interconnection structure is a key part between the electrical device and the printed circuit board as the mechanical fixing and electrical interconnection. Aiming at the difficulties in real-time monitoring and extracting characterization signals for the health status of interconnects,firstly,a degenerate electrical model was established in this paper,by analyzing the failure modes and mechanisms of the QFP interconnect structure. Then, according to the degraded electrical model of the interconnect structure,a real-time monitoring circuit was built,with the charging time of the external capacitor selected as the characterization signal, and the relationship between the electrical parameters of the degradation model and the charging time was established. Afterwards, the Multisim and the development board had been used to simulate and verify the relationship between the equivalent electrical model parameters and the charging time in the degradation process of the interconnect structure. Finally, in order to analyze the degradation process of interconnects,a small system test board was used for random vibration test. From the results,combined with the electron microscope image of the interconnect structure, it was found that the charge time can characterize the failure process and failure mode of the interconnect structure well.
引文
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[3]Kim C U,Bang W H,Xu H,et al. Characterization of sold-er joint reliability using cyclic mechanical fatigue testing[J]. Journal of Metals,2013,65(10):1362-1373.
[4]Che F X,Pang J H L. Study on board-level drop impact re-liability of Sn-Ag-Cu solder joint by considering strain ratedependent properties of solder[J]. IEEE Transactions onDevice and M aterials Reliability,2015,15(2):181-190.
[5]李乐,陈忠,张宪民.复杂背景下X射线BGA焊点气泡检测[J].焊接学报,2015,36(3):80-84+5.Li le,Chen Zhong,Zhang Xianmin. Void defection of sold-er joints under complex X-ray imaging background[J].Transactions of the China Welding Institution,2015,36(3):80-84+5.(in Chinese)
[6] Zhang Junsheng,Wang Mingquan,Wang Yu,et al. Voiddefect detection in BGA solder joints using mathematicalmorphology[J]. Journal of M easurement Science and In-strumentation,2017,8(2):199-204.
[7]吴尘,陈伟元.基于染料渗透试验的BGA焊点失效分析[J].现代制造工程,2016(10):111-114.Wu Chen,Chen Weiyuan. Failure analysis of BGA solderjoints based on dye penetrate testing[J]. M odern M anufac-turing Engineering,2016(10):111-114.(in Chinese)
[8]Lee C J,Chen W Y,Chou T T,et al. The investigation ofinterfacial and crystallographic observation in the Ni(V)/SAC/OSP Cu solder joints w ith high and low silver contentduring thermal cycling test[J]. Journal of M aterials Sci-ence:M aterials in Electronics,2015,26(12):10055-10061.
[9]Li S,Yan Y. Intermetallic growth study at Sn-3. 0 Ag-0. 5Cu/Cu solder joint interface during different thermal condi-tions[J]. Journal of M aterials Science:M aterials in Elec-tronics,2015,26(12):9470-9477.
[10]Tang W,Jing B,Huang Y F,et al. Feature extraction forlatent fault detection and failure modes classification ofboard-level package under vibration loadings[J]. ScienceChina Technological Sciences,2015,58(11):1905-1914.
[11]汤巍,景博,黄以锋,等.温度与振动耦合条件下的电路板级焊点失效模式与疲劳寿命分析[J].电子学报,2017,45(7):1613-1619.Tang Wei,Jing Bo,Huang Yifeng,et al. Analysis of fail-ure modes and life of solder joints under coupling of vi-bration and thermal loads[J]. Acta Electronica Sinica2017,45(7):1613-1619.(in Chinese)
[12]蒋礼,伍晓霞,潘毅,等.基于裂纹扩展的无铅焊点阻抗等效模型[J].电子元件与材料,2011,30(12):54-57+60.Jiang Li,Wu Xiaoxia,Pan Yi,et al. An equivalent imped-ance model for lead-free solder joints based on crack prop-agation[J]. Electronic Components and M aterials,2011,30(12):54-57+60.(in Chinese)
[13]Huang M,Lee C. Board level reliability of lead-free de-signs of BGAs,CSPs,QFPs and TSOPs[J]. Soldering&Surface M ount Technology,2008,20(3):18-25.
[14]董佳岩,景博,黄以锋,等.振动载荷下电路板级焊点失效信号表征及分析[J].半导体技术,2017,42(4):315-320.Dong Jiayan,Jing Bo,Huang Yifeng,et al. Characteriza-tion and analysis of board-level solder joint failure signalsunder vibration load[J]. Semiconductor Technology,2017,42(4):315-320.(in Chinese)